A 1.5-V, 1.5-GHz CMOS low noise amplifier

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork Microgyroscopes

In this paper, the design, implementation and characterization of a continuous time transimpedance-based ASIC for the actuation and sensing of a high-Q MEMS tuning fork gyroscope (TFG) is presented. A T-network transimpedance amplifier (TIA) is used as the front-end for low-noise, sub-atto-Farad capacitive detection. The T-network TIA provides on-chip transimpedance gains of up to 25 MOmega, has a measured capacitive resolution of 0.02 aF/radicHz at 15 kHz, a wide dynamic range of 104 dB in a bandwidth of 10 Hz and consumes 400 muW of power. The CMOS interface ASIC uses this TIA as the front-end to sustain electromechanical oscillations in a MEMS TFG with motional impedance greater than 10 MOmega. The TFG interfaced with the ASIC yields a two-chip angular rate sensor with measured rate noise floor of 2.7deg/hr/radicHz, bias instability of 1deg/hr and rate sensitivity of 2 mV/deg/s. The IC is fabricated in a 0.6-mum standard CMOS process with an area of 2.25 mm² and consumes 15 mW.     

A 1.5 V single-supply one-transistor CMOS EEPROM

Describes a 1.5 V single-supply one-transistor p-channel CMOS EEPROM array which is fabricated with a double polysilicon gate 7-mask CMOS technology. Avalanche injection and Fowler-Nordheim emission are used as very low power programming mechanisms. A thin oxide of 28 nm allows write and erase voltages below -30 V. They are generated on-chip by voltage multipliers and fed by 1.5 V logic circuitry to the matrix array. Results measured on a 16/spl times/4 bit word-erasable test array are presented.     

A 1.5-V full-swing bootstrapped CMOS large capacitive-load drivercircuit suitable for low-voltage CMOS VLSI

This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

A 0.8-μm CMOS technology for high-performance ASIC memory andchannelless gate array

A 0.8-μm polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (±0.2) μm are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8-μm full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail     

一种新颖的1.5 V CMOS 4FSK解调电路

为了减小 4进制频移键控信号 ( 4FSK )解调电路的复杂性 ,提高解调输出的准确性 ,文中提出了一种可以在 1.5V下工作 ,标准 CMOS工艺实现的 4 FSK解调电路。该解调电路采用一个基准电压 ,利用绝对值比较的特性解调出 4 FSK频移键控数字信号     

1.5V低功耗Rail-to-Rail CMOS运算放大器

基于2μm标准P阱CMOS工艺,实现了一种1.5V低功耗Rrail-to-Rail CMOS运算放大器.本运算放大器采用两对跨导器作rail-to-rail输入级,并运用电流折叠电路技术,将最低电源电压降到VT+3VDS.sat.运放同时采用一种适合于低电压要求的对称AB类推挽电路作rail-to-rail输出级,获得了高驱动能力和低谐波失真.芯片测试结果表明,在100pF负载电容和1K负载电阻并联条件下,运放的静态功耗只有270μW,开环电压增益,单位增益带宽和相位裕度分别达到了70dB,2.2MHz和60.     

0.18μm CMOS, Monolithic MSTP ASIC

I. Introduction Motivated by adopting both telecom and data-com traffic into Synchronous Digital Hierarchy (SDH)[1] transport payloads, we develop the mono-lithic Multi-Service Transport Platform (MSTP)[2] Application Specified Integrated Circuit (ASIC) MSEOSX8-6, which is a highly integrated device capable of mapping 10/100/1000Mbit/s Ethernet[3], 155Mbit/s Resilient Packet Ring (RPR)[4], as well as 2.048Mbit/s E1 traffic into SDH STM-1 payloads. On the line side, the chip s…     

A 1.5-V 900-MHz monolithic CMOS fast-switching frequencysynthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm². The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset     

A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver

This paper reports on the realization and the characterization of an application-specific integrated circuit (ASIC) intended for the processing of impulse radio ultra-wideband (IR-UWB) baseband signals. The incoming baseband signals result from the direct down-conversion of IR-UWB radio-frequency pulses, which are modulated by a binary frequency-shift keying (BFSK) scheme. The realized mixed-signal integrated circuit features an analog demodulation based on the quadricorrelation method, a non-coherent pulse detector using an integrate-and-dump operation and a bit-level synchronization digital circuit. An novel acquisition algorithm intended for low duty-cycled IR-UWB signals enabling a signal-to-noise ratio (SNR) estimate is proposed. The baseband ASIC is able to demodulate, acquire and decode BFSK IR-UWB signals. It requires 13 mW of supply power during the initial acquisition and 6.5 mW during the signal tracking phase at a pulse repetition rate (PRR) of 5 MHz. The circuit is fabricated in a 0.18-$mu{hbox {m}}$ CMOS technology.      

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clockgeneration

This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-μm triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is ±150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100     

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-μm foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the ~43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is ~23 mW     

Metastability behavior of CMOS ASIC flip-flops in theory and test

Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules     

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25-μm CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V     

1.5 V power supply CMOS voltage squarer

A CMOS voltage squarer for low voltage applications is proposed. The circuit works with a 1.5 V power supply and provides a THD of <3% with input signals up to 260 mV_pp. A 0.3% lower THD is achieved with input signals up to 120 mV_pp     

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.