共查询到20条相似文献,搜索用时 218 毫秒
1.
2.
本文在PSPICE电路模拟的基础上设计了一套GaAs IC对阈值电压均匀性要求的计算方法,并计算三种不同GaAs IC对阈值对电压均匀性的要求,结果表明,SDFL对阈值电压均匀性的要求较低,σVth为218mV,DCFL和BDCFL对阈值电压均匀性要求较高,σVth分别为38mV和35mV。模拟计算还提出;优化和未优化的电路对阈值电压均匀性的要求不同;工艺不同,电路对阈值电压均匀性的要求也不同。这 相似文献
3.
4.
给出了对DCFL电路单元的研究,包括电路设计和用先进的P埋层自对准栅工艺制作电路的实验结果。表明它可以适用于大规模GaAsDCFL电路的设计和制造。 相似文献
5.
直接耦合场效应逻辑(DCFL)具有简单的结构、良好的速度/功耗性能,是GaAsFETLSI电路中一种重要的逻辑形式。传统E/D型DCFL电路具有较低的成品率和较差的温度特性,本文研究了改进的E/E型DCFL电路。对E/D、E/E型DCFL电路的直流、瞬态及温度特性进行了分析、模拟和比较,E/E逻辑具有良好的高温性能。经优化设计,最后制作出单门延迟约100ps、单门功耗约1mW的E/D和E/E型DCFL电路,且E/E型电路较E/D型电路具有更高的成品率。 相似文献
6.
7.
直接耦合场效应逻辑(DCFL)具有简单的结构、良好的速度/功耗性能,是GaAs FETLSI电路中一种重要的逻辑形式。传统E/D型DCFL电路具有较低的成品率和较差的温度特性,本文研究了改进的E/E型DCFL电路。对E/D、E/E型DCFL电路的直流、瞬态及温度特性进行了分析、模拟和比较,E/E逻辑具有良好的高温性能。经优化设计,最后制作出单门延迟的100ps、单门功耗的1mW的E/D和E/E型D 相似文献
8.
9.
傅炜 《固体电子学研究与进展》1994,14(1):22-27
利用GaAsMESFET功率特性的线性化模型,求出GaAsMESFET近似最佳功率负载阻抗,为利用谐波平衡法计算提供初值。然后,使用自行研制的谐波平衡分析软件包,进行GaAsMESFET大信号模型参数的提取和非线性电路模拟计算。将两只总栅宽为9.6mm的GaAsMESFET管芯,利用内匹配功率合成技术,在C波段(5.5~5.8GHZ)制成1dB压缩功率大于8W,典型功率增益9dB的GaAsMESFET内匹配功率管。 相似文献
10.
11.
Kawano R. Yamanaka N. Oki E. Yasukawa S. Okazaki K. Ohki A. Usui M. Sato N. Katsura K. Ando Y. Kagawa T. Hikita M. 《Advanced Packaging, IEEE Transactions on》2001,24(1):91-98
For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface 相似文献
12.
在数字系统的同步接口设计中,可编程逻辑器件的输入输出往往需要和周围新片对接,些时I/O接口的时序问题显得尤为重要。介绍了几种FPGA中的I/O时序优化设计的方案,切实有效的解决了I/O接口中的时序同步问题。 相似文献
13.
Xuezhe Zheng Lexau J.K. Bergey J. Cunningham J.E. Ron Ho Drost R. Krishnamoorthy A.V. 《Photonics Technology Letters, IEEE》2007,19(7):453-455
Combining the strengths of both proximity communication and optical communication, a new hybrid input-output (I/O) platform delivers on-chip bandwidth off-chip and over distance. We demonstrate, for the first time, a four-channel hybrid I/O interface by integrating proximity communication and vertical-cavity surface-emitting-laser-based parallel optical interconnects on the same commercial 90-nm complementary metal-oxide-semiconductor platform. The optical I/O can operate at 5 Gb/s per channel, and the complete hybrid I/O interface achieved 2.5 Gb/s per channel. We characterize the I/O link performance for various data rates and chip separations, and show 10-mum chip separation tolerance for proximity communication 相似文献
14.
一种信号处理机的高速I/O接口结构 总被引:3,自引:0,他引:3
肖国有 《微电子学与计算机》1993,10(1):20-22
本文介绍了一种以TMS320C25为核心的信号处理机的高速I/O接口.在数据流图分析的基础上,讨论了高速I/O接口的功能与性能要求,重点分析了I/O接口的硬件结构及其功能的实现原理,该I/O接口可以与PC机配合构成独立的、通用的数据采集处理与分析系统. 相似文献
15.
16.
17.
18.
19.
Performance considerations in designing network interfaces 总被引:5,自引:0,他引:5
Design issues that affect the performance of network input/output (I/O) are examined by analyzing the design and performance of a workstation's network interface to the 100-Mb/s FDDI token ring. Several design alternatives for partitioning functions between the network interface and the host software are evaluated. A simple model is proposed for looking at the performance of network I/O, and an effective analysis approach for predicting user-perceived throughput is demonstrated. The analysis reveals that, particularly for network interfaces that reside on an I/O bus, providing a DMA engine for data movement provides significant improvements in throughput. However, the designs for the receive and transmit sides are not necessarily symmetrical, and it is shown that host architecture considerations influence the design of each direction differently. The analysis is used to show the potential benefits of having all protocol functions on the network interface and also to point out the potential processing power needed on that network interface 相似文献