Electro-thermal circuit simulation using simulator coupling

The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electro-thermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. In contrast to other known simulator couplings a time step algorithm is used, Its implementation in simulation tools is described. The thermal modeling of the die/package structure and the extended modeling of the electronic circuit is discussed. Simulation results which indicate the capabilities of the methodology for electro-thermal simulation are compared to experimental results     

Electro-thermal short pulsed simulation for SOI technology

This work investigates the determination of thermal boundary conditions for electro-thermal simulations in case of short duration stressing event for SOI devices. An analysis of the heat flow inside the structure is given showing an important thermal role of contacts in deep submicron SOI devices. These boundary conditions are applied to ISE simulations of a partially depleted 130nm SOI diode during an ESD event and a good matching with TLP experimental results has been obtained.     

Identification of plasma-induced damage conditions in VLSI designs

Typically, the plasma charging effect is investigated by using antenna test structures that do not replicate well enough conditions occurring in real VLSI integrated circuits (ICs). Consequently, understanding, modeling, and detection of plasma-charging-induced gate oxide damage in real IC's is often inadequate. This paper discusses a new plasma-charging monitoring technique that assesses the extent of the above problem. This technique employs a multiplexed antenna monitoring (MAM) test structure with 400+ antenna configurations to determine the dependency between IC layout and the extent of gate oxide damage. The paper reports the results of application of this technique to a 0.35-μm, 75-Å gate oxide, CMOS technology. The obtained results lead to a new definition of “antenna ratio” that is supposed to capture plasma-charging conditions in real VLSI circuits     

Electro-thermal characterization and simulation of integrated multi-trenched XtreMOSTM power devices

This paper presents a new methodology to characterize and simulate the electro-thermal aspects of packaged power drivers using multi-trenched XtreMOS^TM devices. Electrical device data is collected by pulsed and DC measurements. Thermal data is collected through on-chip sensors and through a full surface high resolution transient interferometric mapping (TIM). For the first time a data driven segmented electro-thermal transient model is proposed to accurately describe the thermal profile behavior for the mutli-trenched devices. Further investigations of the thermal heating impact on the driver due to the low thermal conductivity of the trenches (SiO₂) have been carried out. The results of the investigations have been discussed for two different gate to source (VGS) bias conditions: VGS below the temperature compensation point (TCP), which is a bias condition that might lead to a thermal runaway, and VGS above TCP.     

Electro-thermal simulation of metal interconnections under high current flow

The present paper deals with an electro-thermal simulator able to foresee the electrical and thermal parameters of any shaped metal interconnection driven by constant current in a single-layer PCB. This proposed simulator is composed by the cyclic interaction between an electrical solver for the calculation of the current density as well as heating power density distributions and a thermal solver based on the recently proposed steady state analytical thermal simulator DJOSER [4]. In a metal interconnection, because of the temperature dependence of the resistivity, the self Joule-heating within the metal, the heating due to proximity of power devices, the packaging structure and the various thermal boundary conditions concur to change the temperature distribution and the local conductivity values within the interconnection, so that the usual hypothesis of isothermal substrate is largely unrealistic. The simulations were performed on a virtual single-layer PCB in FR-4 epoxy glass cloth with a 80 μm thick copper-foil interconnection driven with constant current. The results, showed in terms of distribution maps of current density, voltage potential, heating power density and temperature, were compared with those obtained under isothermal conditions for many values of the input current and under different average convective heat-transfer coefficients.     

SWEC speeds VLSI simulation

A new simulator called SWEC (StepWise Equivalent Conductance) can efficiently simulate circuits with MOS transistors and passive elements. SWEC adopts four novel techniques: 1) stepwise equivalent conductance implicit integration, 2) piecewise-linear waveform event-driven simulation, 3) recursive convolution formulation based on the Pade approximation, and 4) interconnect partition, to achieve significant speed-ups over existing simulators. The first two timing simulation techniques are briefly reviewed in this article     

Modeling and simulation of VLSI digital systems

Discrete simulation of digital circuits is a vital tool in the design process. However, few people are aware of the modeling assumptions inherent in discrete simulation. Nor is there a widely accepted and consistent theory of modeling and simulation of discrete/digital systems. In this paper we concentrate on the basic ideas behind discrete modeling and present a discussion of the most popular algorithms used in writing simulators. In addition, we use the characteristics of discrete models to define the logic, functional, and behavioral levels of simulation. In closing, we discuss new issues in modeling and simulation.     

Optimization of device area and overall delay for CMOS VLSI designs

This paper addresses specific design tradeoffs that should be considered relative to CMOS VLSI designs using gate-array, semi-custom, or full-custom implementations. The main focus is on design optimization for speed and device area and on meeting the on-chip load drive requirements using one- and two-dimensional expansion techniques. Detailed comparisons are made between the effectiveness of the various design options in their ability to yield a specific performance within speed and/or area constraints while driving on-chip loads with and without geometrical constraints. These comparisons result in a number of design curves that cover the range of full CMOS custom design, for which two-dimensional scaling can be optimally utilized, to those cases involving semi-custom and gate-array designs for which geometric constraints exist (fixed height cells or fixed device sizes). A figure of merit is defined that relates speed and area to each specific circuit implementation, indicating that it can be used to make an effective comparison between overall performance and design option. It is finally suggested that a chip layout approach can be adopted that is useful for implementing any of the design options discussed.     

Parallel bit-level pipelined VLSI designs for high-speed signal processing

This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in designing such fully pipelined architectures. These include clock skew, clock distribution networks, buffering, timing simulation, area overhead due to pipelining, and testing. A total of six bit-level pipelined designs, including a multiplier, an FIR filter block, and a multichannel multiply-accumulate/add chip, have now been fabricated in CMOS technology. These chips have been tested both for functionality and speed. The results of these tests and the applications of these chips are presented and discussed.     

Electro-thermal simulation including a temperature distribution inside power semiconductor devices

The idea of including non-uniform temperature distribution into power semiconductor device models is not new, as accurate electro-thermal simulations are required for designing compact power electronic systems (as integrated circuits or multi-chip modules). Electro-thermal simulations of a PIN-diode based on the finite-element method, show a non-uniform temperature distribution inside the device during switching transients. Hence the implicit assumption of a uniform temperature distribution when coupling an analytical electrical model and a thermal model yields inaccurate electro-thermal behaviour of the PIN-diode so far. If literature reports procedures regarding complex thermal network modelling, few papers address the problem of mixing adequately electrical and thermal issues. Instead of using a one-dimensional finite difference or element method, the bond graphs and the hydrodynamic method are used to build a 1D electro-thermal model of the PIN-diode. The paper focuses on electrical issues and the proper expression and localization of power losses to feed the thermal network model. The results by this original technique are compared with those given by a commercial finite-element simulator. The results are similar but the computation effort attached to the proposed technique is a fraction of that required by finite-element simulators. Moreover the proposed technique may be applied easily to other power semiconductor devices.     

Optimizing VLSI interconnect model for SPICE simulation

The importance of matching the frequency range for electromagnetic analysis and circuit simulation of VLSI interconnects is discussed in this paper. The electromagnetic analysis utilizes Helmholtz equation to calculate eddy-current loss and dielectric loss. Modeling is based on assembling filters with high cutoff frequencies and small numbers of components. The performance of a gate-array interconnect at different clock frequencies is analyzed.     

Topography-dependent electrical parameter simulation for VLSI design

A postprocessor for calculating the step crossing resistance and interlayer capacitance from device cross sections from SAMPLE simulation or SEM profiles is presented. An approximate curvilinear square algorithm is used for rapid evaluation of the two-dimensional equivalent number of lateral squares to an accuracy of a few percent. Studies of resistance for single steps and linear gaps are used to determine rules of thumb for resistance dependence on aspect rations, sidewall slope, and facet size. Studies of interlayer capacitance show the importance of reflow shape and the nonscalable sidewall capacitance component. Typical topography effects for today's devices show a fourfold increase in the two-dimensional RC product contribution to signal delay relative to planar structures. New deposition technologies which provide better step coverage are shown to be necessary to improve the scalability of signal delay. A meanderline test structure is used to verify the accuracy of resistance simulation and explore a new bias-sputtering technology.     

Calibrating simulation tools for nanometer designs

Next-generation silicon processes will challenge system-on-a-chip (SOC) designers to increase the accuracy of the data they feed to their high level tools. Minimum circuit features of 250 nm (0.25 μm) or below are demanding. The tools that simulate them will need transistor models and interconnect parameters that reflect nothing less than the actual physical properties of the process in which ICs are to be manufactured. These silicon-calibrated models can then pass their accuracy on to capable transistor-level simulation tools. Silicon calibration calls for for tighter relationships and more effective communication than is now found among silicon foundries electronic design automation (EDA) companies, and IC design groups. The EDA tools must be regularly updated, to equip design engineers to cope with the challenges of nanometer design. Although simulation tools may never predict silicon behavior with 100 percent accuracy, EDA tool vendors and IC fabrication facilities share a responsibility to calibrate their tool suites as closely as possible with actual silicon     

Simulation of complete VLSI fabrication processes withheterogeneous simulation tools

An integrated environment for the simulation of VLSI fabrication processes is presented. Emphasis is put on automated operation to achieve maximum efficiency in TCAD deployment. Addressing the increasing number and diversity of process steps in state-of-the-art semiconductor fabrication processes, mechanisms have been devised to support the smooth, automatic interaction of heterogeneous simulation tools with multiple data formats in the context of large-scale experiments for global calibration, device optimization, and yield improvement tasks. For maximum versatility, the operation of the environment is either controlled via a graphical user interface, a batch file, or a combination of the two. It is possible to submit predefined analysis tasks for background execution, while still being able to monitor and control operation and to access and view simulation data interactively. Split-lot experiments are performed on workstation clusters in parallel operation, delivering the desired results in the shortest possible time. The TCAD environment presented offers server functionality for running large number of complex simulations. At the same time, it supports the design and seamless integration into the environment of client task applications     

The accuracy and validity of the simulation of VLSI MOS transistors

Corrections of the concepts of the accuracy and validity of compact models of deep submicron MOS transistors are suggested for the circuit design of VLSIs.     

A comprehensive two-dimensional VLSI process simulation program, BICEPS

Bell Integrated Circuit Engineering Process Simulator (BICEPS) is a comprehensive VLSI process-simulation program developed at Bell Laboratories. BICEPS incorporates the most up-to-date physical models and efficient numerical algorithms to make it a highly robust and general-purpose program. BICEPS can calculate doping profiles resulting from ion implantation, predeposition, oxidation, and epitaxy in one or two spatial dimensions as well as etching and deposition of oxide, nitride, and photoresist. In this paper, the physics of IC process simulation will be reviewed with an emphasis on the various physical models implemented in BICEPS. Calculation of the impurity profiles in VLSI devices involves the solution of a coupled set of nonlinear time-dependent partial differential equations, with moving boundaries and in more than one spatial dimension. The numerical techniques in obtaining a solution to this problem, namely, spatial discretization, time discretization, and the treatment of moving boundaries are also described in this paper. The capabilities of BICEPS are illustrated by the results of simulation of the fabrication of a typical NMOS transistor.