A 220-MSample/s CMOS Sample-and-Hold Circuit Using Double-Sampling

In this paper a brief overview of the electro-thermal simulation based on the method of simultaneous iteration is given, through the example of the SISSI (Simulator for Integrated Structures by Simultaneous Iteration) package. The modular approach used for the layout-based electro-thermal netlist generation is described. This approach allows an easy implementation of package model libraries. The capabilities of SISSI are introduced by simulation examples where in most cases the results are compared to measurement results.     

Electro-thermal circuit simulation using simulator coupling

The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electro-thermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. In contrast to other known simulator couplings a time step algorithm is used, Its implementation in simulation tools is described. The thermal modeling of the die/package structure and the extended modeling of the electronic circuit is discussed. Simulation results which indicate the capabilities of the methodology for electro-thermal simulation are compared to experimental results     

Fully coupled dynamic electro-thermal simulation

Fully coupled dynamic electro-thermal simulation on chip and circuit level is presented. Temperature dependent thermal conductivity of silicon is taken into account, thus solving the nonlinear heat diffusion equation. The numerical solution is carried out by using the industry-standard simulator SABER, therefore for electro-thermal simulations we are able to use the common electrical compact models by adding a heat source and thermal pins to them. The application of this technique and need for electro-thermal simulation is illustrated with the simulation of a current control circuit built into a multiwatt package     

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

CMOS集成电路的自热效应和均匀温度分布的电热耦合模拟

集成电路实际是由相互耦合的电学子系统和热学子系统共同组成。本文基于具体的封装结构提出集成电路的热学分析模型,分析了温度对集成电路性能和功耗的影响。并且针对均匀温度分布的集成电路,采用解耦法实现了电热耦合模拟软件ＥＴｓｉｍ。     

用有限差分法实现集成电路的电热耦合模拟

文章详细介绍了一种用于集成电路自热效应研究的电热耦合模拟软件(ETsira2)。针对具体的集成电路封装结构以及特定的封装材料，该软件利用有限差分数值算法(FDM)，求解三维热扩散方程；对集成电路芯片进行了精确的三维热学分析和电学性能验证。     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

Thermoelectrical modelling and simulation of devices based on VO2

Limits of development of conventional silicon-based integrated circuits get closer. More and more effort is done to develop new devices for integrated circuits. A promising structure is based on the semiconductor-to-metal phase change of vanadium-dioxide at about 67 °C. In these circuits the information is carried by combined thermal and electrical currents. For device modelling and circuit design, accurate distributed electro-thermal transient simulation is mandatory. This paper is the first one to present an electro-thermal transient simulation method for VO₂ devices operating in real-world conditions. The paper presents three VO₂ material models, the algorithmic extension of an electro-thermal field simulator to be able to handle hysteresis and the transient simulation issues of VO₂ and the modelling of VO₂ based devices. The paper compares measured and simulated device characteristics.     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

Simulation of LED based luminaires by using multi-domain compact models of LEDs and compact thermal models of their thermal environment

Fast and accurate prediction of hot lumens of LEDs installed in luminaires is an important step in the design of robust and reliable products. A possible approach to this is to create a multi-domain circuit model of a complete LED chip + package + luminaire system that can be simulated by any Spice-like circuit simulator with electro-thermal capabilities. Many LED chip and LED package models and modeling techniques have been published recently, but compact thermal modeling of luminaires as multi heat-source system was not yet dealt with in the literature. This paper aims to fill this gap be describing a systematic approach for system (luminaire) level analysis aimed at solving the combined thermal, electrical and light output simulation problem consistently by describing a method for creating a compact thermal model of LED luminaries with an approach borrowed from the layout based electro-thermal simulation of analog ICs. The applicability of the described method is demonstrated with a real life example, including the validation of the results with thermal measurements.     

Fast field solver for the simulation of large-area OLEDs

Lighting purpose organic light-emitting devices need special engineering because of the high electrical and thermal requirements of the operation. Our electro-thermal field simulation software is better to satisfy these special demands than the widely used commercial tools. This article surveys the special simulation needs of lighting purpose OLEDs, presents the electro-thermal extension of the FDM-based SUNRED thermal field simulator and the significant algorithmic changes for speed up the program and make it more flexible. The simulation of an existing OLED closes the paper.     

Electro-thermal simulation including a temperature distribution inside power semiconductor devices

The idea of including non-uniform temperature distribution into power semiconductor device models is not new, as accurate electro-thermal simulations are required for designing compact power electronic systems (as integrated circuits or multi-chip modules). Electro-thermal simulations of a PIN-diode based on the finite-element method, show a non-uniform temperature distribution inside the device during switching transients. Hence the implicit assumption of a uniform temperature distribution when coupling an analytical electrical model and a thermal model yields inaccurate electro-thermal behaviour of the PIN-diode so far. If literature reports procedures regarding complex thermal network modelling, few papers address the problem of mixing adequately electrical and thermal issues. Instead of using a one-dimensional finite difference or element method, the bond graphs and the hydrodynamic method are used to build a 1D electro-thermal model of the PIN-diode. The paper focuses on electrical issues and the proper expression and localization of power losses to feed the thermal network model. The results by this original technique are compared with those given by a commercial finite-element simulator. The results are similar but the computation effort attached to the proposed technique is a fraction of that required by finite-element simulators. Moreover the proposed technique may be applied easily to other power semiconductor devices.     

CMOS集成电路的电热耦合效应及其模拟研究

文章基于集成电路具体的封装结构提出了它的热学分析模型。针对均匀温度分布的集成电路,采用解耦法实现了电热耦合模拟软件Etsim,并研究分析了温度对集成电路性能和功耗的影响。     

Testing analogue functions using m-sequences

A prototype systems level approach to testing embedded analogue functions in VLSI circuits is described. The technique is self-contained and can be used for wafer, package and field testing. The technique can be easily integrated into a digital test environment. The fault detection capabilities of the method are demonstrated by simulation results.<>     

Thermal design and characterization of a modular integrated liquid cooled 1200 V-35 A SiC MOSFET bi-directional switch

The aim of this work is the thermal design of a modular direct liquid cooled package for 1200 V–35 A SiC power MOSFETs, in order to take full advantage of the high power density and high frequency performance of these devices, in the development of a modular integrated solution for power converters. An accurate electro-thermal fluid dynamic model is set up and validated by thermal characterization on a prototype; numerical models have been used to study the internal temperature distribution and to propose further optimization.     

Thermally-aware modeling and performance evaluation for single-walled carbon nanotube-based interconnects for future high performance integrated circuits

Given the performance and reliability limits of conventional copper interconnects in the tens of nanometer regime, carbon-nanotube (CNT) based interconnects emerge as a potential reliable alternative for future high performance VLSI industry. In this paper, we present an accurate thermally-aware model for single-walled carbon-nanotube (SWCNT) based interconnects. Our thermally-aware model is an integration of temperature-dependent electrical parasitics model and thermal equivalent circuit that captures both self-heating and heat conduction phenomena. We verify the accuracy of our electro-thermal model against recently reported experimental measurements. By leveraging the presented electro-thermal model, we present a simulation platform to estimate the performance of SWCNT-based interconnects under different temperature conditions. Our thermally-aware model achieves improvement in the delay estimation accuracy of about 51.3% on average. Based on our simulation results, SWCNT-based interconnects offer more than 5×reduction in delay at dimensions of about 10-20 nm for 27- 127 °C temperature range.