模拟电路结构化可测性设计研究综述

本文说明模拟电路结构化可测性设计(DFT)的原则,同时介绍了两个可测性设计结构。这些原则和结构可以作为数模混合测试总线标准IEEE P1149.4的基础。     

VLSI可测性设计研究

从可测性设计与VLSI测试、VLSI设计之间的关系出发，将与可测性设计相关的VLSI测试方法学、设计方法学的内容有机地融合在一起。文中简要地介绍了VLSI可测性设计的理论基础和技术种类，简明地评述了可测性设计的现状和发展趋势，并且探讨了可测性设计的实现方法。     

一种压缩可测性设计的研究实现

本文针对固定管脚芯片可测性设计中测试向量庞大和测试时间过长问题,提出了一种有效的压缩可测性设计,改进了传统并行扫描测试设计。该设计方法在SMIC 0.18μm工艺下一款电力载波通信芯片设计中验证,仿真结果表明压缩扫描可测性设计能有效减少测试向量数目,从而减小芯片测试时间。     

高频锁相环的可测性设计

边界扫描是数字电路常用的测试技术，基于IEEE1149．1标准的边界扫描技术对一款CMOS高频锁相环进行了可测性设计，该锁相环最高工作频率达GHz。详细讨论了最高输出频率、输出频率范围和锁定时间参数的测试方案，给出了详细的测试电路和测试方法。对应用该测试方案的锁相环电路增加测试电路前后的电路网表进行了Hspice仿真，仿真结果证明该方法能有效测量锁相环的参数，并且对原锁相环电路的功能影响很小。该测试方法可广泛用于高频锁相环的性能评测和生产测试。     

一种电路板网络化诊断测试的可测性设计方法

提出并实现了一种电路板网络化诊断测试的可测性设计方法.按照此方法设计的电路板,除了能够实现上电自检,还可以借助无线或有线网络由异地PC(个人电脑)机等远地终端来启动电路板测试、控制测试过程、查看测试流程、获得测试结果以及更新/升级测试程序,对电路板进行全面的诊断测试.为电路板的高质量测试提供了一条实用、有效的技术途径.     

模拟电路故障可测性数值判断

本文讨论模拟电路故障可测性问题。提出了以矩阵数值秩为依据的故障可测性数值判断方法,给出了考虑容差扰动及数值计算误差时的故障可测性条件。根据可测性分析与设计的不同要求,将可测性条件分解为拓扑条件和数值限制两个方面描述。文献[1]给出了拓扑条件,本文对数值限制作了讨论,给出了可测性数值判据。     

一款百万门缀SOC芯片的可测性设到

本文介绍了一款基于65nm工艺的数字处理芯片的可测性设计,采用了边界扫描测试,存储器内建自测试和内部扫描测试技术。这些测试技术的使用为该芯片提供了方便可靠的测试方案,实验结果表明该设计的测试覆盖率符合工程应用要求。     

BiCMOS电路可测性设计探讨

本文提出了ＢｉＣＭＯＳ电路的实用可测性设计方案，该方法与传统方法相比，可测性高，硬件花费小，仅需额外添加一个ＭＯＳ管和两个控制端，就可有效地用单个测试码测出ＢｉＣＭＯＳ电路的开路故障和短路故障，减少了测试生成时间，可广泛应用于集成电路设计中。     

一种DC-DC芯片内建可测性设计

DC-DC芯片设计中有许多内部参数需要检测和控制，有限的引脚数目使得直接测试内部参数比较困难. 文中提出一种通用性很强的内建可测性设计方法，在芯片内部设计时只需要增加规模较小的测试电路，就可以在芯片外引脚上测量芯片内部众多的参数.     

模拟电路的振荡测试技术

集成电路设计和制造技术的发展给电路测试带来了巨大的挑战,其中模拟电路的测试是电路测试的难点.目前在这一领域有许多致力于降低测试难度,节约测试成本的研究.介绍了一种称为"振荡测试"的模拟电路测试技术,从振荡电路的构造、测试响应的测量和分析等方面综述了振荡测试技术的研究现状,同时总结了振荡测试技术的优点,分析了当前存在的局限性,并对将来的发展进行了展望.     

Low-Voltage Analog Circuits Based on Wideband Capacitive Coupling

A technique for wideband low-voltage analog circuit operation based on capacitive signal coupling is discussed. Circuits based on this technique do not show the GB degradation of other low-voltage approaches based on floating-gate transistors. The technique is validated with simulations of a new CMOS mixer and experimental results of a test chip in a 0.5 m CMOS technology.     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.     

模拟电路故障诊断可信度研究

提出了描述标称转移矩阵Ｚ０的各标征向量几何分布性状的Ｖｏｒｏｎｏｉ多胞体，定义了描述测量向量ｄＵ在标征向量Ｚｉ中位置的标征干扰角θｕｉ。然后利用这两个概念揭示了容差─故障电路可诊充要和充分条件，讨论了定位故障的极值法和阈值法的有效性、局限性，及提高定位准确率的可能途径。     

基于极零点灵敏度的模拟电路可测性分析

介绍了基于模拟电路极零点灵敏度的分析方法,给出了极零点灵敏度的计算公式。介绍了模拟电路可测性度量的概念,以及基于极零点灵敏度的模拟电路可测性分析方法,给出了求可测性度量的方法。该方法可以用于确定模拟电路的测试点和测试方法。作为例子,对一个3阶电路进行了简要分析。     

数模混合电路的PCB设计

高速PCB的设计中,数模混合电路的PCB设计中的干扰问题一直是一个难题。尤其模拟电路一般是信号的源头,能否正确接收和转换信号是PCB设计要考虑的重要因素。文章通过分析混合电路干扰产生的机理,结合设计实践,探讨了混合电路一般处理方法,并通过设计实例得到验证。     

“模拟集成电路”课程教学内容的探讨

本文将"模拟集成电路"课程定位为后端专业课程,提出了从最新科研文献中提取课程内容的方法。本文以代表当今研究前沿的2010年"模拟集成电路"最重要学术会议的论文集为素材,通过分析和总结素材中涉及的概念,得出"模拟集成电路"教学应该覆盖的内容,并将所获得的课程与模拟集成电路界知名大学的现有模拟集成电路教学体系进行了比较。     

Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits

This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.     

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor

We have developed an analog circuit fault diagnostic system based on Bayesian neural networks using wavelet transform, normalization and principal component analysis as preprocessors. Our proposed system uses these preprocessing techniques to extract optimal features from the output(s) of an analog circuit. These features are then used to train and test a neural network to identify faulty components using Bayesian learning of network weights. For sample circuits simulated using SPICE, our neural network can correctly classify faulty components with 96% accuracy.