A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet

A 3.125-Gb/s clock and data recovery (CDR) circuit using a half-rate digital quadricorrelator frequency detector and a shifted-averaging voltage-controlled oscillator is presented for 10-Gbase-LX4 Ethernet. It can achieve low-jitter operation and improve pull-in range without a reference clock. This CDR circuit has been fabricated in a standard 0.18-/spl mu/m CMOS technology. It occupies an active area of 0.6 /spl times/ 0.8 mm/sup 2/ and consumes 83 mW from a single 1.8-V supply. The measured bit-error rate is less than 10/sup -12/ for 2/sup 7/ - 1 PRBS 3.125-Gb/s data. It can meet the jitter tolerance specifications for the 10-Gbase-LX4 Ethernet application.     

A 2.5-Gb/s 15-mW clock recovery circuit

This paper describes the design of a 2.5-Gb/s 15-mW clock recovery circuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation. In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions. Fabricated in a 20-GHz 1-μm BiCMOS technology, the circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz     

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.     

10Gb/s突发模式时钟数据恢复电路设计

突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器,分析了其工作原理与性能,以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证,芯片面积为675?m ? 625?m。测试结果表明,该电路可以即时的实现10Gbit/s的突发数据恢复,恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit insilicon bipolar technology

A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for nonlinear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a -3.6-V supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 2²³-1 pseudorandom bit sequence     

70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing

The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively.     

A 40-Gb/s clock and data recovery circuit in 0.18-/spl mu/m CMOS technology

A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-/spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps/sub rms/ and 9.67 ps/sub pp/ with a PRBS of 2/sup 31/-1 while consuming 144 mW from a 2-V supply.     

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz fT silicon bipolar technology

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f _T self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III-V technologies     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm². The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

A 2.5-Gb/s clock and data recovery IC with tunable jittercharacteristics for use in LANs and WANs

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs     

一种误码率为10-12的750MHz半数字结构时钟和数据恢复电路的研究

A semi-digital clock and data recovery (CDR) is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1P8M CMOS process, our CDR is integrated into a high speed serial and de-serial (SERDES) chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.     

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.     

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in×1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA     

A monolithic 156 Mb/s clock and data recovery PLL circuit using thesample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2²³-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor