防御差分功耗分析攻击技术研究

差分功耗分析(DPA)攻击依赖于密码芯片在执行加密/解密过程中功耗与数据及指令的相关性,利用统计学等方法对收集到的功耗曲线进行分析,盗取关键信息,对密码芯片的安全性构成极大威胁。防御DPA攻击技术的开发与研究,已经成为信息安全领域的迫切需求。该文在归纳DPA攻击原理的基础上,对主流防御DPA攻击技术的理论与设计方法进行概述与分析,指出防御DPA前沿技术的研究进展。重点讨论防御DPA攻击技术的原理、算法流程和电路实现,包括随机掩码技术、功耗隐藏技术、功耗扰乱技术等等,并详细分析这些技术存在的优缺点。最后,对该领域潜在的研究方向与研究热点进行探讨。     

一种新型的抗DPA攻击可配置逻辑结构

DPA(Differential Power Analysis)攻击的强度取决于芯片电路功耗与所处理的数据之间的相关性以及攻击者对算法电路实现细节的了解程度.本文结合动态差分逻辑和可配置逻辑的特点,提出了一种具有抗DPA攻击能力的双端输出可配置逻辑(DRCL:Dual-Rail Configurable Logic)....     

FPGA密码芯片改进掩码防护方法研究

功耗攻击已对密码芯片物理安全性构成严峻威胁,对其攻击和防御的研究是密码旁路分析的热点问题。文中给出了一种DES伪随机掩码算法的设计和实现方法,分析了算法抗功耗攻击的安全性。结果表明:一般的DES伪随机掩码算法只能抵抗一阶差分功耗攻击,不能有效防御二阶差分功耗攻击。为抵御二阶DPA攻击,采用掩码方法对DES掩码算法结构进行了改进,在理论上具有抗DPA攻击的能力。     

分组密码线性部件的抗功耗攻击特性

通过对FPGA实现的分组密码SM4进行实际攻击,发现了SM4的线性部件使其具有抗差分功耗攻击的能力,研究并归纳了一般分组密码中线性部件的结构特性和其抗功耗攻击能力的关系,从而提出了一种针对分组密码的算法设计层面的功耗攻击防护措施.完成了对硬件实现的国密SM4算法的成功的DPA攻击.     

差分功率分析攻击中的信号对齐方法研究

针对差分功耗分析(DPA)攻击的原理及特点,分析了未对齐信号对DPA攻击的影响.论述了现在已知的对未对齐信号的频域和模式识别处理方法,分别分析了它们的原理及优缺点,提出了在时域内对未对齐信号采用分段处理进行对齐的方法.通过实验验证了该方法的正确性及有效性,该方法能够有效的处理未对称信号,提高DPA攻击的效率,减少DPA攻击的样本量.     

智能卡RSA算法DPA的攻击与防御

智能卡在执行算法过程中会泄露一些能耗信息,采用差分能量分析(DPA)利用这些信息可以分析出加密的密钥,其危害远大于传统的数学分析手段.本文对算法级DPA攻击RSA算法方法和已有的算法级防止DPA攻击方法进行了研究,并在此基础上提出一种三重掩盖法来全面防御针对RSA算法的DPA攻击,且进行了仿真,效果明显.     

基于FPGA加密芯片的DPA实现与防御研究

差分功耗分析是破解AES密码算法最为有效的一种攻击技术,为了防范这种攻击技术本文基于FPGA搭建实验平台实现了对AES加密算法的DPA攻击,在此基础上通过掩码技术对AES加密算法进行优化与改进。通过实验证明改进后的AES算法能有效的防范DPA的攻击。     

智能卡抗DPA的硬件解决方案研究

智能卡在执行算法过程中泄露功耗信息.差分功耗分析(DPA)者利用这些信息就可以分析出加密的密钥,其危害远大于传统的数学分析手段.目前有很多软件的手段来防止差分功耗分析,但这些方法相对比较复杂.本文针对硬件层次的几种防差分功耗分析的方法进行了分析研究.     

一种改进的CRT-RSA防御侧信道攻击算法

针对Ha等人提出的CRT-RSA防御算法进行了分析,指出其算法在使用中国剩余定理（CRT）的过程中仍然存在着降低计算效率的模逆运算.为了提高计算性能消除模逆运算,基于明文掩盖方法,提出了一种改进的安全CRT-RSA防御算法,并通过对改进算法的理论分析,证明该算法可抵抗现有已知的功耗攻击（SPA、DPA、RDA和（N-1）攻击）和故障攻击（FA）且不存在模逆运算,从而更加高效与实用.     

防DPA攻击的标准单元库的设计与实现

给出了一个功耗恒定标准单元库的设计实现方法,并利用该标准单元库实现了DES密码算法中的S-盒。实验结果表明,这种标准单元库能够很好地起到防DPA攻击的作用。     

Practical Second‐Order Correlation Power Analysis on the Message Blinding Method and Its Novel Countermeasure for RSA

Recently power attacks on RSA cryptosystems have been widely investigated, and various countermeasures have been proposed. One of the most efficient and secure countermeasures is the message blinding method, which includes the RSA derivative of the binary‐with‐random‐initial‐point algorithm on elliptical curve cryptosystems. It is known to be secure against first‐order differential power analysis (DPA); however, it is susceptible to second‐order DPA. Although second‐order DPA gives some solutions for defeating message blinding methods, this kind of attack still has the practical difficulty of how to find the points of interest, that is, the exact moments when intermediate values are being manipulated. In this paper, we propose a practical second‐order correlation power analysis (SOCPA). Our attack can easily find points of interest in a power trace and find the private key with a small number of power traces. We also propose an efficient countermeasure which is secure against the proposed SOCPA as well as existing power attacks.     

智能卡差分能量分析实验平台实现与数据优化

随着密码学和密码芯片的广泛应用,针对密码芯片的攻击也日益增多.差分能量分析（Differential Power Analysis,DPA）攻击是最常见的一种侧信道攻击方法.DPA攻击者无须了解加密算法的具体细节,而只通过密码设备的能量迹分析即可破解出设备的密钥.因此,研究DPA攻击十分必要.实现了智能卡DPA实验系统,并对于此系统的能量迹测量数据进行优化处理,从而更有利于针对此类攻击的分析和相应防御措施的设计.     

The research of DPA attacks against AES implementations

This article examines vulnerabilities to power analysis attacks between software and hardware implementations of cryptographic algorithms. Representative platforms including an Atmel 89S8252 8-bit processor and a 0.25 um 1.8 v standard cell circuit are proposed to implement the advance encryption standard （AES）. A simulation-based experimental environment is built to acquire power data, and single-bit differential power analysis （DPA）, and multi-bit DPA and correlation power analysis （CPA） attacks are conducted on two implementations respectively. The experimental results show that the hardware implementation has less data-dependent power leakages to resist power attacks. Furthermore, an improved DPA approach is proposed. It adopts hamming distance of intermediate results as power model and arranges plaintext inputs to differentiate power traces to the maximal probability. Compared with the original power attacks, our improved DPA performs a successful attack on AES hardware implementations with acceptable power measurements and fewer computations.     

DES芯片抵御高阶差分功耗分析攻击方法研究

分析独特的屏蔽方法及改进方法的不足,提出了逻辑层和算法层相结合抵御高阶差分功耗分析攻击的新方法,并给出芯片半定制设计流程.芯片关键部分电路采用自定义功耗恒定逻辑单元实现,非关键部分电路采用CMOS逻辑以减少功耗和面积.整体电路采用独特的屏蔽方法自定义轮实现.结果表明芯片能够抵御高阶差分功耗分析攻击,运算速度与现有方法相当,而所需资源比现有方法少.     

Pseudo 4D projective coordinate-based multi-base scalar multiplication

In order to address the problem of elliptic curve cryptosystem (ECC) for the expensive cost in scalar multiplication and the vulnerability to the power analysis attacks,a pseudo 4D projective coordinate-based multi-base scalar multiplication was proposed to optimize group operation layer and scalar multiplication operation layer,which aimed at increasing the performance of ECC and resisting common power analysis attacks.Experimental results show that compared with the state-of-the-art algorithms,the proposed algorithm decreases 5.71% of point doubling cost,3.17% of point tripling cost,and 8.74% of point quintupling cost under discrete group operations.When the key length is 160 bit,the proposed algorithm decreases 36.32% of point tripling cost,17.42% of point quintupling cost,and 8.70% of the system cost under continuous group operations.The analyzing of power consumption wave shows that the proposed algorithm can resist SPA and DPA attack.     

A table masking countermeasure for low-energy secure embedded systems

Future wireless embedded devices will be increasingly powerful, supporting many more applications, including one of the most crucial, which is security. Although many embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. This paper presents a table masking countermeasure to resist differential power analysis (DPA) and differential electromagnetic analysis (DEMA). Real power and EM measurements are used to verify the countermeasure using second- and third-order DPA and DEMA attacks on a popular low-energy embedded ARM processor. Results show that the new table masking countermeasure provides increased security without large overheads of energy dissipation compared with previous countermeasures. With the emergence of security applications personal digital assistants, cellphones, and other embedded devices, low-energy countermeasures for resistance to DPA/DEMA are crucial for supporting future wireless embedded systems.     

An online power allocation algorithm based on deep reinforcement learning in multibeam satellite systems

Dynamic power allocation (DPA) is the key technique to improve the system throughput by matching the offered capacity with that required among distributed beams in multibeam satellite systems. Existing power allocation studies tend to adopt the metaheuristic optimization algorithms such as the genetic algorithm. The achieved DPA cannot adapt to the dynamic environments due to the varying traffic demands and the channel conditions. To solve this problem, an online algorithm named deep reinforcement learning‐based dynamic power allocation (DRL‐DPA) algorithm is proposed in this paper. The key idea of the proposed DRL‐DPA lies in the online power allocation decision making other than the offline way of the traditional metaheuristic methods. Simulation results show that the proposed DRL‐DPA algorithm can improve the system performance in terms of system throughput and power consumption in multibeam satellite systems.     

Symmetric Adiabatic Logic Circuits against Differential Power Analysis

We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual‐rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data‐independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.