基于神经网络方法预测薄膜的厚度

首次利用前馈三层神经网络模型,建立了场发射薄膜的膜厚的神经网络预测模型,用金刚石薄膜的膜厚数据进行验证.结果表明,该模型预测的相对误差小于6.1％.     

聚合物发光器件的旋涂膜厚模型研究

聚合物膜厚的控制对于优化聚合物发光器件的光电性能是至关重要的.应用最小二乘法,通过对中心复合设计实验数据的拟合,建立了旋涂法制备聚合物薄膜的膜厚回归模型.测试结果表明:利用该模型所得到的预测膜厚与旋涂的实测膜厚基本相符.膜厚模型的建立,对于旋涂工艺中旋涂条件的选择、薄膜厚度的控制以及器件性能的优化具有一定的实用价值.     

紫外可见光谱法测量光刻胶的膜厚

在液晶显示器的制造过程中,光刻是极为重要的制造工艺过程之一。将厚的独立的负胶膜或者将光刻胶涂敷在二氧化硅衬底上以后,可以测量其膜厚,因为光刻胶膜厚决定其光刻工艺的工艺条件。能够快速地测量光刻胶的膜厚,是液晶显示器制造过程的先决性工作的一部分。文章提出了测量上述光刻胶膜厚的新方法,即利用紫外可见吸收光谱法中的Beer-Lambert定律来确定膜厚。在我们的研究中,采用acrylic负胶作为基质(resin) ,它分别具有50μm和100μm的膜厚。在350 nm时,50μm的薄膜的最大吸收为0 .728 ,而100μm的最大吸收为1 .468 5。而在正胶的研究中,采用novolac作为基质(resin)。它的膜厚通常是1 ～5μm。在紫外可见吸收光谱测膜厚的实验中,当重氮荼醌的吸收波长为403 .8 nm时,5 .93μm厚的薄膜的最大吸收为1 .757 4 ,其膜厚是由扫描电镜测得的。而另一个正胶薄膜在403 .8 nm的最大吸收为0 .982 3 ,其薄膜厚度计算得到为3 .31μm。利用这些数据,我们得到了这两种光刻胶薄膜的紫外可见吸收光强与其膜厚关系的两个校准曲线。     

(Li,Mg):ZnO薄膜的溶胶-凝胶法制备及特性表征

利用溶胶-凝胶旋涂制膜方法制备了具有良好表面形貌及c轴择优取向性的(Li,Mg):ZnO薄膜.重点研究了该法制膜时不同膜厚(Li,Mg):ZnO薄膜的结构及光学性质.扫描电子显微镜(SEM)图像及X射线衍射(XRD)图谱分析结果表明随着膜厚的增加,薄膜晶粒尺寸逐渐增大,薄膜的晶化程度及c轴择优取向性增强.但薄膜厚度的增加是有一定范围的,当薄膜厚度过大时,薄膜均匀性、致密性及c轴择优取向性显著下降.样品的荧光光致发光(PL)谱表明,Mg的掺入使近紫外发光峰出现了蓝移,恰当膜厚的(Li,Mg):ZnO薄膜发光特性主要以深能级发射(DLE)为主,蓝绿发光峰强度很高.     

磁控溅射不同厚度铝薄膜的微结构及其表面形貌

用直流磁控溅射法在室温的Si(100)基底上制备了21～55 nm范围内不同厚度的铝膜,并用X射线衍射和扫描电镜对薄膜的结构和表面形貌进行了表征.分析结果表明:制备的铝薄膜呈多晶状态,晶粒择优取向为(111),随着膜厚的增加,Al(100)衍射峰宽变窄,薄膜的平均晶粒尺寸逐渐增大,晶面间距逐渐减小,薄膜中的残余应力减小.膜厚为55 nm时,Al膜均匀致密.     

Na/Mg共掺ZnO薄膜的溶胶-凝胶法制备及特性研究北大核心CSCD

利用溶胶-凝胶旋转涂膜法在耐热玻璃衬底上制备了不同膜厚的Na/Mg共掺ZnO薄膜。重点研究了膜厚对Na/Mg共掺ZnO薄膜结构和光学特性的影响。扫描电子显微镜（SEM）图像和X射线衍射（XRD）图谱分析结果表明,膜厚为200~500 nm时,随着膜厚的增加,薄膜的结晶性、致密性及c轴择优取向生长特性都呈现出先增强后降低的趋势。透射光谱分析结果表明,薄膜在可见光范围内的平均透光率随着膜厚的增加而显著下降。实验条件下,膜厚约为300 nm的Na/Mg共掺ZnO薄膜具有优良的结构特性和透光特性。荧光光致发光（PL）谱表明该薄膜中缺陷很少,是优良的紫外发光材料。     

非晶金刚石与非晶碳化锗复合增透保护膜系的设计与实现

为了有效保护硫化锌等红外光学元件并提高其在工作波段的透过率,根据薄膜光学原理进行增透设计,从而获得膜系光学参数;采用射频磁控溅射技术制备非晶碳化锗薄膜,通过调整甲烷流速比调整薄膜的折射率,根据流速比和沉积时间控制膜厚,再用过滤阴极真空电弧技术制备非晶金刚石薄膜,分别改变衬底偏压和沉积时间控制薄膜的折射率和膜厚.利用光谱椭偏仪和台阶仪表征薄膜折射率和膜厚,通过小角X射线反射和X射线光电子谱测试非晶金刚石薄膜的密度和非晶碳化锗薄膜中的锗含量,使用纳米压痕仪和傅里叶红外透射谱仪确定薄膜的硬度和红外透过率.试验表明,非晶金刚石和非晶碳化锗薄膜的折射率分别与薄膜的密度和薄膜中的锗含量密切相关,非晶金刚石与非晶碳化锗复合膜系是硫化锌等红外光学元件性能优异的增透保护膜.     

磁控溅射薄膜厚度分布模拟软件的编制

对平面磁控溅射薄膜厚度分布提出了一种理论计算模型，编制了磁控溅射薄膜厚度分布模拟软件系统ＭＦＴＤＳ，并用ＭＦＴＤＳ对半球壳形工件内外膜厚分布进行了计算机模拟，在受磁控靶溅蚀区不均匀性影响较小的部位，所得膜厚分布结果与实验数据基本吻合     

酞菁铜蒸发镀膜工艺中膜厚控制参数的确定

基于目前采用的膜厚仪中缺少必要的有机材料的参数(密度和声阻抗),采用真空蒸镀法,在抛光硅片上蒸镀不同显示值厚度下的酞菁铜薄膜,利用椭偏仪测量其真实膜厚,并使用数学软件MATLAB,结合膜厚仪实时监控原理进行理论计算,拟合得到酞菁铜薄膜的参数——声阻抗Zf=0.01 g/cm3.s,薄膜密度Df=6.68 g/cm3。验证实验结果表明,此参数输入膜厚仪中可以比较精确地控制薄膜厚度,显示值和实际测量值的差距约为3 nm。     

磁控溅射Cu膜的织构与残余应力

用磁控溅射工艺在不同沉积温度制备200 nm与2μm厚的Cu膜,并用X射线衍射仪(XRD)与光学相移方法测量薄膜织构与残余应力.结果表明,对于200 nm厚Cu膜,随着沉积温度T增加,晶粒取向组成几乎保持不变,薄膜具有较低拉应力且不断减小;而对于2μm厚Cu膜,随着T增加,Cu<111>/Cu<200>晶粒取向组成比值急剧减小.薄膜具有较大的拉应力且不断减小.根据表面能、应变能及缺陷形成等机制对薄膜残余应力与织构的演化特征进行了分析.     

Thermal peeling stress analysis of thin-film high-TC superconductors

Thermal peeling stress between a thin film and the substrate is caused by the mismatch of thermal expansion coefficients while the film and substrate undergo a temperature change. The thermal peeling stress resulting from the temperature decrease from ambient to operating conditions (cryogenic temperatures) between a thin-film high-temperature superconductor and its substrate is calculated using finite element analysis (FEA). The superconductor thin film is idealized as a long bridge on a large substrate. A two-dimensional FEA model is applied to calculate the tensile (peeling) stress at the thin film/substrate interface. Results are obtained for different geometries and temperature conditions, and these results are compared with analytical predictions. A stress singularity is found at the very edge of the thin film which is not predicted by the analytical prediction. The peeling stress can be very high due to this stress singularity, even if the temperature change is not large. The stress singularity area depends on the local geometry of the edge, suggesting that refining the geometry of the thin-film HTS device is important.     

Prediction of the Thickness of a Thin Paint Film by Applying a Modified Partial-Least-Squares-1 Method to Data Obtained in Terahertz Reflectometry

We applied a multivariate analysis method to time-domain (TD) data obtained in terahertz (THz) reflectometry for predicting the thickness of a single-layered paint film deposited on a metal substrate. For prediction purposes, we built a calibration model from TD-THz waveforms obtained from films of different thicknesses but the same kind. Because each TD-THz wave is approximate by the superposition of two echo pulses (one is reflected from the air–film boundary and the other from the film–substrate boundary), a difference in thickness gives a relative peak shift in time in the two echo pulses. Then, we predicted unknown thicknesses of the paint films by using the calibration model. Although any multivariate analysis method can be used, we proposed employing a modified partial-least-squares-1 (PLS1) method because it gives a superior calibration model in principle. The prediction procedure worked well for a moderately thin film (typically, several to several tens of micrometers) rather than a thicker one.     

Simulation of ultra thin film SOI transistors using a non-local ballistic model for impact ionisation

To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the “Lucky electron” theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.     

Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states

An analytical drain current model for a-Si:H TFTs obtained by considering deep and tail states simultaneously is presented. Using an effective temperature approach, the localised deep and tail states have been considered in the DC model such that no approximations are needed. As verified by the published data, this analytical DC model provides an accurate prediction of the drain current characteristics of an a-Si:H thin film transistor.<>     

功能梯度薄膜的脉冲激光沉积研究进展

介绍了功能梯度薄膜材料的特点和应用 ;比较了功能梯度薄膜常用制备方法 ;概括了功能梯度薄膜制备中的掺杂技术并给出了脉冲激光沉积功能梯度薄膜的模型 ;论述了脉冲激光沉积技术在制备功能梯度薄膜材料方面的应用与最新进展     

Stability of thin film resistors - Prediction and differences base on time-dependent Arrhenius law

Thin film resistors are widely used in electronic industry. Analogue technique requires a certain precision from the components and a good prediction of what change can happen during application. This paper presents a method for prediction of resistive value changes due to ageing for any relevant condition in the temperature-time-expanse. The method is based and derived from the Arrhenius’ equation. Three new characteristics for stability prediction and evaluation of thin film resistors are introduced: temperature dependence of drift f(t)R, drift potential ln(ΔR/R)_pot, and temperature of absolute stability T_stab. Differences and influencing parameter of material and processes on thin film resistor manufacturing will be discussed.     

IC工艺中互连薄膜晶粒生长的实验和理论模型

通过研究不同淀积温度下铝互连薄膜的晶粒形态 ,研究晶粒的生长规律。建立理论模型描述加热过程中薄膜晶粒的行为 ,可据此进行工艺模拟 ,对 IC制造工艺进行事前评估。根据薄膜晶粒生长的机理 ,得到晶粒尺寸和温度及时间的关系。由于薄膜晶粒的生长使表面能减小 ,晶粒的平均尺寸随生长时间增大。对晶粒尺寸的观察证实晶粒大小近似对数正态分布     

On the Homogenization of Multilayered Interconnect for Interfacial Fracture Analysis

The interface crack problem for Cu/low-k interconnect is considered using global-and-local finite element analysis. In the global analysis the thin film interconnect is represented by a homogenized layer with equivalent material properties. Local model around the interface crack tip is analyzed with displacement boundary condition extracted from the global modeling result to determine the fracture mechanics parameters. It is shown that, for the global-and-local modeling approach, interconnect homogenization using representative volume element (RVE) approach provides accurate prediction on the fracture mechanics parameters for an interface crack under either thermal or mechanical loads, while significant error occurs when the interconnect, even though having thickness less than 1/100 of the whole component thickness, is neglected in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal excursion is also investigated as an application example of the global-and-local modeling approach.     

Accurate negative bias temperature instability lifetime prediction based on hole injection

Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO₂ film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO₂. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (=Q_hole/J_inj0), accurate lifetime prediction in terms of the V_th shift is realized, and by analyzing of relationship between I_D reduction and V_th shift, accurate lifetime prediction in terms of the I_D reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.