A hardware accelerator for two-dimensional image analysis

This paper describes the architecture and operation of a new hardware accelerator called MultiRing for performing various geometrical operations on two-dimensional image space. This hardware architecture is shown to be applicable for design rule checking in VLSI layout and many image processing operations including noise suppression and contour extraction. It has both a fast execution speed and extremely high flexibility. Each row data stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 20 basic instructions each ring cycle, which gives MultiRing maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of MultiRing was confirmed by successfully running a software simulator having one-to-one structural correspondence to the MultiRing hardware.     

Construction of parallel and distributed static simulation system based on augmented reality

This article puts forward a kind of parallel and distributed static augmented scene system structure to improve the performance of real time augmented simulation system.Based on static registration technique,several groups of processing nodes do parallel scene pictures taking,3D registration and virtual-real merging.Process on different nodes is controlled by uniform synchronization mechanism and network transmitting.Wide field of view image can be obtained from image mosaic operation and displayed by wide view display system.Detailed system architecture,registration algorithm,method how to determine camera position and synchronization mechanism between each process node are introduced.The experiment result can validate the good performance of the designed system.     

利用FPGA的高性能向导滤波器设计

向导滤波器是近几年出现的一种边缘保持的滤波算法,在图像平滑、细节增强、去雾等方面已有广泛应用。提出了一种单图像向导滤波器的VLSI 结构,整个设计采用全流水线结构,不需要任何片外存储器,且实现了图像尺寸、滤波窗口大小等参数的灵活在线调整。实验结果表明,该结构的逻辑资源和内存需求较低,低端FPGA即可满足要求,在Altera的Cyclone Ⅲ系列FPGA上每秒可处理100帧1 0241 024的图像,完全满足实时处理的要求。因此,所提出的结构既可为PC机提供硬件加速,也可用于嵌入式系统的前端,实现各种实时图像处理功能。     

A VLSI Architecture for Image Registration in Real Time

Image registration is an ubiquitous task occurring in countless image analysis applications. A dedicated implementation of image registration algorithms is the best approach to meet the intensive computation requirements of implementing image registration schemes in real time. This paper presents an efficient VLSI architecture for real-time implementation of image registration algorithms using an exhaustive search method. Normalized cross correlation function, mean square error, and blue screen technique algorithms are implemented for image registration. The architecture is based on a data flow design that allows sequential inputs but performs parallel processing. Based on the architecture, a programmable chip can be designed for image registration. Chips can be cascaded to achieve better performance and sizes of both the search and the reference image which can vary with time from a small to a very large value.     

基于互信息和梯度的红外与可见光图像配准新方法

红外与可见光图像配准是常见的多传感器图像配准,在军事、遥感等领域有着广泛的应用。提出了一种基于互信息和图像梯度的红外与可见光图像的自动配准方法：首先,获得图像的梯度信息,然后根据定义的扩展结构获得边缘区域图像,选择最大归一化互信息作为相似性测度,使用Powell算法获得最佳配准参数。实验结果证明,本文方法较传统的基于互信息和梯度的配准方法,提高了配准的速度和精度,可以作为一种有效的粗配准的方法。     

Merging VLIW and vector processing techniques for a simple,high-performance processor architecture

This paper proposes a new processor architecture called VVSHP for accelerating data-parallel applications, which are growing in importance and demanding increased performance from hardware. VVSHP merges VLIW and vector processing techniques for a simple, high-performance processor architecture. One key point of VVSHP is the execution of multiple scalar instructions within VLIW and vector instructions on unified parallel execution datapaths. Another key point is to reduce the complexity of VVSHP by designing a two-part register file: (1) shared scalar–vector part with eight-read/four-write ports 64×32-bit registers (64 scalar or 16×4 vector registers) for storing scalar/vector data and (2) vector part with two-read/one-write ports 48 vector-registers, each stores 4×32-bit vector data. Moreover, processing vector data with lengths varying from 1 to 256 represents a key point for reducing the loop overheads. VVSHP can issue up to four scalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results to be written back into VVSHP register file. However, it cannot issue more than one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to data memory. The design of our proposed VVSHP processor is implemented using VHDL targeting the Xilinx FPGA Virtex-5 and its performance is evaluated.     

基于GPU的星图配准算法并行程序设计

星图配准是星图处理应用中的一个重要步骤,因此星图配准的速度直接影响了星图处理的整体速度.近几年来,图形处理器(GPU)在通用计算领域得到快速的发展.结合GPU在通用计算领域的优势与星图配准面临的处理速度的问题,研究了基于GPU加速处理星图配准的算法.在已有配准算法的基础上,根据算法特点提出了相应的GPU并行设计模型,利用CUDA编程语言进行仿真实验.实验结果表明:相较于传统基于CPU的配准算法,基于GPU的并行设计模型同样达到了配准要求,且配准速度的加速比达到29.043倍.     

Minimal-memory bit-vector architecture for computational mathematical morphology using subspace projections.

Computational mathematical morphology (CMM) is a nonlinear filter representation particularly amenable to real-time image processing. A windowed, translation-invariant filter is represented by a set of less-than-or-equal decisions that are executed by a parallel arrangement of comparators. In the state-of-the-art implementation, each pixel value of a windowed observation is indexed into separate lookup tables to retrieve a set of bit vectors which are "anded" together to produce a bit vector with a unique nonzero bit. The position of that bit is used to look up a filter value in a table. The number of stored bit vectors is proportional to the number of image gray levels. An architecture for CMM is presented that uses a minimal number of bit vectors so that required memory is less sensitive to the number of gray levels. The number of pixels in the observation window is the dimension of the image space. In the proposed architecure, basis elements are projected to subspaces of the image space and only bit vectors unique to each subspace are stored. Each projection corresponds to a subspace partition. Filter memory is greatly reduced by using intermediate lookup tables to map observations to unique bit vectors. We investigate two possible projection strategies: A fixed, singleton architecture, in which each subspace is one dimension, and a minimal architecture, in which a large number of subspace projections are searched for, one with minimal memory. Insensitivity to the number of gray levels is demonstrated through simulated, random-image space tessellations. We also present memory savings in a digital photocopier application.     

Image Segmentation Using Information Bottleneck Method

In image processing, segmentation algorithms constitute one of the main focuses of research. In this paper, new image segmentation algorithms based on a hard version of the information bottleneck method are presented. The objective of this method is to extract a compact representation of a variable, considered the input, with minimal loss of mutual information with respect to another variable, considered the output. First, we introduce a split-and-merge algorithm based on the definition of an information channel between a set of regions (input) of the image and the intensity histogram bins (output). From this channel, the maximization of the mutual information gain is used to optimize the image partitioning. Then, the merging process of the regions obtained in the previous phase is carried out by minimizing the loss of mutual information. From the inversion of the above channel, we also present a new histogram clustering algorithm based on the minimization of the mutual information loss, where now the input variable represents the histogram bins and the output is given by the set of regions obtained from the above split-and-merge algorithm. Finally, we introduce two new clustering algorithms which show how the information bottleneck method can be applied to the registration channel obtained when two multimodal images are correctly aligned. Different experiments on 2-D and 3-D images show the behavior of the proposed algorithms.     

基于改进蚁群算法和互信息的多光谱图像的配准

基于互信息的配准算法有精度高,自动化程度高,不需要对图像进行预处理等优点,已经被大量应用于多光谱图像配准中.但是在计算互信息时,出现了很多局部极值,这就为目标函数的寻优过程带来了很大的困难.提出了一种基于蚁群算法的配准参数寻优方法,改进蚂蚁在每层节点间的转移准则以及全局信息素的更新策略.实验证明,此方法不需要人工干预,对参数的初始值没有依赖性,配准成功率高.     

Adaptive Grid Generation Based Non-rigid Image Registration using Mutual Information for Breast MRI

In this paper a new approach for non-rigid image registration using mutual information is introduced. A fast parametric method for non-rigid registration is developed by adjusting divergence and curl of an intermediate vector field from which the deformation field is computed using finite-central difference method. Mutual information is newly employed as the similarity measure in the gradient-based cost minimization (or mutual information maximization) of the existing registration framework. The huge amount of data associated with MRI is handled by a fully automated multi-resolution scheme. The adaptive grid system naturally distributes more grids to deprived areas. The positive monitor function disallows grid folding and provides a mean to control the ratio of the areas between the original and transformed domain. The flexibility of the adaptive grid allocation could dramatically reduce processing time with quality preserved. Mutual information facilitates robust registration between different image modalities. Different types of joint histogram estimation are compared and integrated with the system. This scheme is applied on dynamic contrast-enhanced breast MRI, which requires the registration algorithm to be non-rigid, contrast-enhanced features preserving. Preliminary experiments show promising results and great potential for future extension.     

Real-time processing and compression of DNA microarray images.

In this paper, we present a pipeline architecture specifically designed to process and compress DNA microarray images. Many of the pixilated image generation methods produce one row of the image at a time. This property is fully exploited by the proposed pipeline that takes in one row of the produced image at each clock pulse and performs the necessary image processing steps on it. This will remove the present need for sluggish software routines that are considered a major bottleneck in the microarray technology. Moreover, two different structures are proposed for compressing DNA microarray images. The proposed architecture is proved to be highly modular, scalable, and suited for a standard cell VLSI implementation.     

A generalized divergence measure for robust image registration

Entropy-based divergence measures have shown promising results in many areas of engineering and image processing. We define a new generalized divergence measure, namely, the Jensen-Renyi (1996, 1976) divergence. Some properties such as convexity and its upper bound are derived. Based on the Jensen-Renyi divergence, we propose a new approach to the problem of image registration. Some appealing advantages of registration by Jensen-Renyi divergence are illustrated, and its connections to mutual information-based registration techniques are analyzed. As the key focus of this paper, we apply Jensen-Renyi divergence for inverse synthetic aperture radar (ISAR) image registration. The goal is to estimate the target motion during the imaging time. Our approach applies Jensen-Renyi divergence to measure the statistical dependence between consecutive ISAR image frames, which would be maximal if the images are geometrically aligned. Simulation results demonstrate that the proposed method is efficient and effective.     

基于MATLAB的超声检测自动判伤算法研究

为了实现MATLAB对超声波检测的自动判伤以及简化图像处理过程,以火车轮对为例,对火车轮对的超声检测B扫描图进行了分类处理。运用基于互信息的图像配准方法对复杂背景图像进行处理,并对基于互信息配准得到的结果进行求补集,最后经过MATLAB工具实现对图像中缺陷的判别并予以标示,显示缺陷的位置信息,成功地实现了超声检测中缺陷的自动判伤,提高了超声检测中的判伤效率。     

GPU Accelerated Generation of Digitally Reconstructed Radiographs for 2-D/3-D Image Registration

Recent advances in programming languages for graphics processing units (GPUs) provide developers with a convenient way of implementing applications which can be executed on the CPU and GPU interchangeably. GPUs are becoming relatively cheap, powerful, and widely available hardware components, which can be used to perform intensive calculations. The last decade of hardware performance developments shows that GPU-based computation is progressing significantly faster than CPU-based computation, particularly if one considers the execution of highly parallelisable algorithms. Future predictions illustrate that this trend is likely to continue. In this paper, we introduce a way of accelerating 2-D/3-D image registration by developing a hybrid system which executes on the CPU and utilizes the GPU for parallelizing the generation of digitally reconstructed radiographs (DRRs). Based on the advancements of the GPU over the CPU, it is timely to exploit the benefits of many-core GPU technology by developing algorithms for DRR generation. Although some previous work has investigated the rendering of DRRs using the GPU, this paper investigates approximations which reduce the computational overhead while still maintaining a quality consistent with that needed for 2-D/3-D registration with sufficient accuracy to be clinically acceptable in certain applications of radiation oncology. Furthermore, by comparing implementations of 2-D/3-D registration on the CPU and GPU, we investigate current performance and propose an optimal framework for PC implementations addressing the rigid registration problem. Using this framework, we are able to render DRR images from a 256×256×133 CT volume in ～?24 ms using an NVidia GeForce 8800 GTX and in ～?2 ms using NVidia GeForce GTX 580. In addition to applications requiring fast automatic patient setup, these levels of performance suggest image-guided radiation therapy at video frame rates is technically feasible using relatively low cost PC architecture.     

An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000

In this paper, we propose an efficient pipeline architecture for the DWT 9/7 filter defined in JPEG 2000. The proposed architecture is composed of column and row processors to perform the separable 2-D DWT. Based on the rescheduling DWT algorithm, we derive a new data flow graph to shorten the critical path. The proposed 1-D column processor requires less pipeline registers to achieve about the same critical path compared with other lifting-based architectures. For the row processor, the data dependency of each lifting step is reduced to only two computation nodes and therefore more pipeline registers can be applied to achieve higher processing speed without increasing the internal memory size in the 2-D case. That is, for an N × N image, it only requires 4N internal memory to perform the row-wise transform. For the memory bit-width analysis, we use software simulation to reduce the memory bit-width for various compression ratios. Since a portion of information from least significant bits of DWT coefficients would be discarded after EBCOT-tier2 processing, one can decrease the data width of internal memory to perform various compression ratios of JPEG 2000 coding, especially at the low-bit rates. Our simulation results suggest that it is practically possible to design the energy-aware memory architecture to further reduce the power consumption in the future work.     

Evaluating similarity measures for brain image registration

Evaluation of similarity measures for image registration is a challenging problem due to its complex interaction with the underlying optimization, regularization, image type and modality. We propose a single performance metric, named robustness, as part of a new evaluation method which quantifies the effectiveness of similarity measures for brain image registration while eliminating the effects of the other parts of the registration process. We show empirically that similarity measures with higher robustness are more effective in registering degraded images and are also more successful in performing intermodal image registration. Further, we introduce a new similarity measure, called normalized spatial mutual information, for 3D brain image registration whose robustness is shown to be much higher than the existing ones. Consequently, it tolerates greater image degradation and provides more consistent outcomes for intermodal brain image registration.     

红外与可见光图像实时配准融合系统

描述了一个自主研制的基于实时分布式多处理机的图像配准和融合系统的设计与实现方案。本系统是具有并行计算机体系结构的通用高速实时图像融合处理系统,选择VxWorks实时操作系统和VEM64x总线的软硬件平台,采用AD公司新型的TS101DSP处理器为核心,多DSP处理器分布并行进行处理,完成多源图像实时高速配准和融合需要进行的大量运算,CPLD芯片完成了采集控制以及多传感器视频同步。由于采用了基于高性能DSP的实时嵌入式系统和通用标准化总线结构设计,该系统可以灵活地应用多种配准和融合算法来实现可见光和红外双通道数字图像的高速实时融合处理,比较好地解决多尺度图像配准融合算法的大数据量计算处理与系统实时性要求之间的矛盾,为多传感器实时图像配准融合处理系统的研制奠定了良好的技术基础。     

基于多核DSP激光成像雷达数据处理系统

采用多核DSP设计了一个用于地面目标检测的激光雷达实时图像处理系统。在详细分析算法各模块资源消耗量的基础上,完成了硬件电路设计,实现了以主辅拓扑结构为框架的软件并行处理系统开发。在系统实现时,先将图像进行分区,并合理地将分区后的图像分配到四个DSP核中进行处理。最后,将并行系统进一步扩展到双核和六核,并与单核系统进行性能比较。对算法运算时间的测试结果表明,系统处理一帧图像仅需50 ms达到了实时性要求。结果表明,对于固定负载的处理系统,单纯地通过增加并行的核数来提高加速比的幅度是有限的。当增加并行的核数已不能明显地提高计算效率时,在系统设计中应着重减少每个核串行运算的负载量。     

Matlab环境下图像配准方法

图像配准是图像处理的重要前期步骤,直接影响图像处理的精度。图像配准应用于多个研究领域,比如医学图像的配准,多数据源遥感图像的配准等。Matlab以其强大的矩阵运算功能及丰富的图像处理函数等,在图像处理方面占有明显的优势。文中阐述了在Matlab环境下图像配准的实现过程,最后对其进行评价。将Matlab与VC编程相结合,可提高运行速度、精度,减少了程序代码,且效果良好。