Plastic encapsulated components for cars

Thermal management in electronics packaging is important. Thermal stress greatly affects reliability and aging of electronic circuits. Our group developed a thermal simulation tool named TRESCOM for investigating thermal problems in electronic packaging. We used this tool for steady-state and dynamic analyses of the thermal qualities of PLCC and CLCC components. Our investigation demonstrated the surprising result that the thermal performance of the plastic encapsulated components is superior to hermetically sealed ceramic components. We conclude that plastic packages are reliable and can compete with ceramic packages at the elevated temperatures that are found in automotive applications     

A comprehensive solution for electronic packages' reliability assessment with digital image correlation (DIC) method

The reliability assessment of electronic packages demands more accurate and efficient method for evaluating heterogeneous packages and their interconnects in various measurement conditions. The digital image correlation (DIC) method has been fully developed in the last decade. With proper improvement, this work demonstrates that DIC method has the ability to fulfill various experimental tasks and obtain the information for interconnect strain analysis, coefficient of thermal expansion (CTE) characterization, in-plane displacement and out-of-plane warpage quantification within one measurement. To some extent, it serves as a comprehensive tool for electronic packages' reliability assessment. Given that the DIC technique is new to the electronic packaging area, this work illustrates the principle of optical non-contact experiment method and presents several improvements to fit for the measurement on electronic packaging area. With these applications, it is foreseeable that the DIC method will play an important role in the reliability assessment of electronic packages.     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

THERMODEL: A Tool for Thermal Model Generation, and Application for MEMS

This paper presents a tool and a method for the generation of reduced order thermal models, in order to assure modeling the effect of the package on the thermal behavior of the packaged device. The method is generic, and can be based either on the simulated or on the measured thermal transient response of the real packages. It is based on the generation of the time constant density spectrum of the thermal response function, from which we automatically generate a reduced order thermal model in the form of an RC ladder network model. Beyond presenting the generic methodology experimental results are also presented, based both on the simulation and measurement of MEMS elements and packages.     

Compact thermal models of packages used in conduction cooledapplications

Results of an extensive study aimed at developing boundary condition independent compact steady-state thermal models of a variety of electronic packages used in conduction cooled applications are presented. Formal mathematical principles were used to establish a nonredundant set of thermal boundary conditions representing board edge and backside cooling with variable board and underfill conductivity. A Design of Experiments approach was employed to reduce the total number of boundary conditions to four, allowing the generation of boundary condition independent CTM's. Two general network topologies, incorporating both simple star-shaped and more complex, shunted networks were developed. To extract the CTM parameters, the thermal networks were optimized using a genetic algorithm-based approach allowing constrained nonlinear global optimization in a standard spreadsheet environment. Comparisons of the accuracy of models from simple to complex are presented for two types of generic parts. It was found that optimized star-shaped CTM's accurately predict junction temperatures, but usually give insufficient accuracy for the heat flows leaving via the package prime lumped surfaces. The inclusion of a floating node allows sufficient degree of freedom to correctly redistribute the heat flows between the “outlet” nodes of the networks. Using the optimization technique, CTM's were derived for thirty parts representing thirteen package families. For most of the packages only network topologies that included a floating node and surface-to-surface links provided satisfactory accuracy. With three different network configurations, for which examples are presented, it was possible to capture the thermal behavior of all the package families investigated     

Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs

Self-heating in silicon-on-insulator (SOI) MOSFETs has become one of the vital issues for design, characterization, optimization and reliability prediction of SOI devices and integrated circuits due to the low thermal conductive buried oxide (BOX) and the continual increase in the microelectronic packaging density. Thermal models that are accurate and detailed enough to provide device temperature profiles and efficient enough for large scale electro-thermal simulation are therefore strongly desirable. This paper discusses the fundamental concepts for modeling of heat flow in semiconductor devices. A brief overview for the conventional approaches to thermal modeling of the SOI devices is given. Improved steady-state and dynamic SOI heat flow models based on the SOI film thermal resistance for efficient prediction of steady-state and dynamic temperature variations in SOI devices are presented. These improved models are applied to investigate temperature distributions and temporal evolution of the junction temperature in SOI nMOSFETs.     

Spectral Caracterization via Fusing Modified Prony Method with High Resolution Nonparametric Spectral Estimators

In this paper, we present a new approach to high-resolution spectral characterization of the unknown number of spectral line components embedded in colored noise. The addressed method resolves the spectral analysis problem via intelligent fusing the two spectrum estimation paradigms: (i) the parametric line spectral estimation that employs the modified regularized Prony (MORP) method for multi-harmonic signal characterization and (ii) nonparametric spectral estimation. Two nonparametric high-resolution spectral estimation methods are proposed to be fused with the MORP: the minimum variance (MV) and maximum entropy (ME) techniques. Via aggregation of the developed model-based MORP and model-free MV/ME techniques into the fused MORP-MV/MORP-ME resulting method a substantial improvement of the spectral characterization performances is gained when those are applied to characterization/analysis of the composed distributed scenes that contain noised closely spaced spectral lines to be localized with high resolution and accuracy. The simulation results are presented to illustrate the performance enhancement gained with the proposed fused MORP-MV/MORP-ME method.     

Dynamic compact thermal models with multiple power sources: application to an ultrathin chip stacking technology

Whereas numerical modeling using finite-element methods (FEM) can provide transient temperature distribution in the component with enough accuracy, it is of the most importance the development of compact dynamic thermal models that can be used for electrothermal simulation. While in most cases single power sources are considered, here we focus on the simultaneous presence of multiple sources. The thermal model will be in the form of a thermal impedance matrix containing the thermal impedance transfer functions between two arbitrary ports. Each individual transfer function element H/sub ij/(s) is obtained from the analysis of the thermal temperature transient at node "i" after a power step at node "j." Different options for multiexponential transient analysis are detailed and compared. Among the options explored, small thermal models can be obtained by constrained nonlinear least squares (NLSQ) methods if the order is selected properly using validation signals. The methods are applied to the extraction of dynamic compact thermal models for a new ultrathin chip stack technology (UTCS).     

Boundary element analysis of thermal fatigue effects on high power IGBT modules

The technology of high power IGBT modules has been significantly improved these last years against thermal fatigue. The most frequently observed failure modes, due to thermal fatigue, are the solder cracks between the copper base plate and the direct copper bonding (DCB) substrate and bond wire lift-off. Specific simulation tools are needed to carry out reliability researches and to develop device lifetime models. In other respects, accurate temperature and flux distributions are essential when computing thermo-mechanical stresses in order to assess the lifetime of high power modules in real operating conditions. This study presents an analysis method based on the boundary element method (BEM) to investigate thermal behavior of high power semiconductor packages subjected to power cycling loads. The paper describes the boundary integral equation which has been solved using the BEM and applied to the case of a high power IGBT module package (3.3 kV–1.2 kA). A validation of the numerical tool is presented by comparison with experimental measurements. Finally, the paper points out the effect on the thermal stress of the IGBT chips position on the DCB substrate. In particular, a light shifting of the silicon chips may be sufficient to delay significantly the initiation and the propagation of the cracks, allowing a higher device lifetime of the studied module.     

Compact thermal modeling for packaged microprocessor design with practical power maps

In this paper, we propose a new behavioral thermal modeling technique for high-performance microprocessors at package level. Firstly, the new approach applies the subspace identification method with the consideration of practical power maps with correlated power signals. We show that the input power signal needs to meet an independence requirement to ensure the model predictability and propose an iterative process to build the models with given error bounds. Secondly, we show that thermal systems fundamentally are nonlinear and then propose a piecewise linear (PWL) scheme to deal with nonlinear effects. The experimental results validated the proposed method on a realistic packaged integrated system modeled by the multi-domain/physics commercial tool, COMSOL. The new piecewise linear models can model thermal behaviors over wide temperature ranges or over different thermal boundary convective conditions due to different fan speeds. Further, the PWL modeling technique can lead to much smaller model order without accuracy loss, which translates to significant savings in both the simulation time and the time required to identify the reduced models compared to the simple modeling method by using the high order models.     

Compact thermal models for stochastic thermal analysis

An effective approach is proposed for constructing compact thermal models for the stochastic thermal analysis of electronics components and packages. This approach exhibits high levels of accuracy for small state space dimensions of the model. The achieved compact thermal models can be used to accurately approximate the stochastic properties not only of junction temperatures but also of the whole space–time temperature rise distribution within the electronics component or package.     

电子封装的简化热模型研究

集成电路的飞速发展使得从封装到电子设备的单位体积功耗和发热量不断增加。电子系统散热问题需要在设计阶段就通过热仿真予以充分考虑和预测。电子封装作为电子系统的最小组成部分,其简化模型的优劣直接影响电子系统热分析的速度和准确性。本文主要讨论单芯片封装稳态简化热模型的建立。先后介绍了从最简单的单热阻模型到目前广为关注的边界条件独立的DELPHI简化模型的结构。其中着重分析了两热阻模型和DELPHI模型的建模方法及过程。     

Compact thermal networks for modeling packages

In this paper, thermal networks for modeling packages are rigorously introduced. A multipoint moment matching method for state space reduction of these discretized thermal networks is formulated. In this manner reduced thermal networks are derived that can be used as boundary condition independent compact thermal models of packages. This algorithm is successfully applied to the detailed analysis of an idealized ball grid array package.     

Thermal Resistance Measurement of LED Package with Multichips

Thermal transient measurements of high power GaN-based light-emitting diodes (LEDs) with multichip designs are presented and discussed in the paper. Once transient cooling curve was obtained, the structure function theory was applied to determine the thermal resistance of packages. The total thermal resistance from junction to ambient considering optical power is 19.87 K/W, 10.78 K/W, 6.77 K/W for the one-chip, two-chip and four-chip packages, respectively. The contribution of each component to the total thermal resistance of the package can be determined from the cumulative structure function and differential structure function. The total thermal resistance of multichip packages is found to decrease with the number of chips due to parallel heat dissipation. However, the effect of the number of chips on thermal resistance of package strongly depends on the ratio of partial thermal resistance of chip and that of slug. Therefore, an important thermal design rule for packaging of high power multichip LEDs has been analogized.     

Thermal modelling of semiconductor packages

This paper presents an improved approach for thermal characterization and simulation of semiconductor packages. The model can significantly reduce the simulation efforts for the design of complex technical thermal systems. It will be shown that the principle of superposition can be used to overcome the problems of thermal resistance narrowings. As the model structure implements a biunique mapping between a special set of border conditions and its parameters, a simple characterization procedure can be applied and the accuracy of the model is found to be independent of the boundary conditions.     

Analysis of thermal impedance for conventional and beam lead IC chips

The thermal impedance of conventional and beam lead IC packages is evaluated from the partial differential equations, which govern the temperature and heat flow within the chip and substrate, and transmission line analogy. The mounting and the geometry dependance of the thermal impedance for various heat sink and chip sizes are presented for both beam lead and conventional IC packages. The variation of thermal impedance with the number of leads and the various Ceramic sizes is shown for the beam lead IC chip.The lumped and the distributed heat sources have been considered for the different mounting structures.     

Novel reworkable fluxing underfill for board-level assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.     

Torsion test applied for reballing and solder paste volume evaluation

Electronic second level interconnect reliability characterization by accelerated thermal-cycling (ATC) test for long-term mission profile is costly and high time consuming. In order to reduce test duration, the torsion test was applied using some specific test parameters to reproduce the same failure modes found in accelerated thermal cycling (ATC) test and in the field. In this paper, we present the torsion test parameters definition and two demonstrations of torsion test application to accelerate reliability characterization of second level interconnect. The first application is the comparison between full SnPb (tin–lead) and reballed LF (lead-free) packages using SnPb balls. In the second the reliability of ceramic BGA solder joints using different solder paste volume was evaluated. In both cases, ATC test results were used as reference. The results suggest that torsion test is a valuable test method and can be applied to evaluate the impact of design and process variations in very short time.