用高阶逻辑表达时态逻辑及其应用

硬件设计的形式化验证技术开辟了对复杂的超大规模集成电路设计进行验证的新途径。高阶逻辑和时态逻辑在形式化验证技术中均得到成功的应用。本文介绍用高阶逻辑表达线性时态逻辑和区间时态逻辑的方法，并以几个简单实例说明它在硬件设计验证中的应用。这种方法的优点是既利用高阶逻辑系统ＨＯＬ的机械化定理证明手段，又发挥了时态逻辑的表达硬件的动态性质的能力。     

复杂非线性电路系统的动力学方程模型

Lagrange和Hamilton运动方程是分析力学的基本原理之一和方法论。应用Lagrange和Hamilton原理建立复杂非线性电路保守动力学方程模型是一种形式化可行的方法。对非保守的动力学系统,定义描述电路系统的荷控支路和链控支路的微观结构概念,应用Hamilton结构的方法,可以得到与La-grange结构等价的方程组;考虑大规模电路系统的复杂性,依据电路系统荷控支路和链控支路微观结构的概念,给出具有控制参量的Lagrange和Hamilton函数,以及具有相应关联矩阵和联接矩阵形式的Lagrange和Hamilton的动态方程;分析了保守和非保守复杂系统拓扑结构关系的描述和其动力学系统的建模,其建模过程具有规范性和方程具有对称性。虽然数学推导过程繁琐,但适合于计算机辅助形式化分析;基于Hamilton方法建立的电路模型为一阶微分动态方程组,特别适合进行理论分析和数值仿真计算。     

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y toπtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.     

量子可逆逻辑电路综合的快速算法研究

可逆逻辑有许多应用,尤其在量子计算领域,量子可逆逻辑电路是构建量子计算机的基本单元,量子可逆逻辑电路综合就是根据电路功能,以较小的量子代价自动构造量子可逆逻辑电路.文中结合可逆逻辑电路综合的多种算法,提出了一种新颖高效的算法,自动构造正极性Reed-Muller展开式(RM),在生成量子可逆逻辑电路的解空间树上,采用总体层次遍历,局部深度搜索,借鉴模板优化技术,构造限界函数快速剪去无解或非最优解的分枝,优先探测RM中的因子,以极高的效率生成最优电路.以国际公认的3变量可逆函数测试标准,该算法不仅能够生成全部最优电路,而且运行速度远远超过同类算法.     

Developing (Meta)Theory of λ-calculus in the Theory of Contexts

We present a case study on the formal development of a non trivial (meta)theory in the Theory of Contexts using the Coq proof assistant. The methodology underlying the Theory of Contexts for reasoning on systems presented in HOAS is based on an axiomatic syntactic standpoint. We feel that one of the main advantages of this approach, is that it requires a very low logical overhead.The object system we focus on is the lazy, call-by-name λ-calculus (λ_cbn), both untyped and simply typed. We will see that the formal, fully detailed development of the theory of (λ_cbn) in the Theory of Contexts introduces a small, sustainable overhead with respect to the proofs “on the paper”. Moreover, this will allow for comparison with similar case studies developed in other approaches to the metatheoretical reasoning in higher-order abstract syntax.     

Emitter-couple logic circuit design based on the threshold-arithmetic algebraic system

Based on the threshold-arithmetic algebraic system which has been proposed for current-mode circuit design,we propose a systematic methodology for emitter-couple logic(ECL)circuit design.Compared to the traditional methodologies and the theory of differential current switches,the proposed methodology uses the HE map and the characteristics of the internal current signals of ECL circuits to determine the external voltage signals.The operations of the HE map are direct and simple,and the current signals are easy to add or subtract,which make this methodology more flexible,direct,and effective,and make it possible to design arbitrary binary and multi-valued logic functions.Two example circuits are designed and simulated by HSPICE using 0.18μm TSMC technology.Simulation results confirm the validity of the proposed methodology.     

基于高阶干扰观测器的极点配置控制器及应用

本文设计了一种可以对外部干扰进行估计的高阶干扰观测器,并针对一类具有外部干扰的单输入单输出离散时间线性系统,提出了一种基于高阶干扰观测器的极点配置控制方法.该方法由常规极点配置控制器和高阶干扰观测器组成.常规极点配置控制器用来保证闭环系统稳定,并将闭环系统的极点配置到理想位置,高阶干扰观测器用来补偿外部干扰对闭环系统的影响.理论分析以及仿真和水箱液位系统中的实验结果表明了所提方法的有效性和优越性.     

Analog Circuit Verification: a State of an Art

Extending formal verification methodology toward analog circuits is a very challenging task that will occupy researchers for some time. To put this challenge in context we sketch some of the history of digital circuit verification as well as more recent attempts to adapt it to continnuous and hybrid systems.     

Automatically Identifying Calling-Prone Higher-Order Functions of Scala Programs to Assist Testers

For the rapid development of internetware, functional programming languages, such as Haskell and Scala, can be used to implement complex domain-specific applications. In functional programming languages, a higher-order function is a function that takes functions as parameters or returns a function. Using higher-order functions in programs can increase the generality and reduce the redundancy of source code. To test a higher-order function, a tester needs to check the requirements and write another function as the test input. However, due to the complex structure of higher-order functions, testing higher-order functions is a time-consuming and labor-intensive task. Testers have to spend an amount of manual effort in testing all higher-order functions. Such testing is infeasible if the time budget is limited, such as a period before a project release. In practice, not every higher-order function is actually called. We refer to higher-order functions that are about to be called as calling-prone ones. Calling-prone higher-order functions should be tested first. In this paper, we propose an automatic approach, namely Phof, which predicts whether a higher-order function of Scala programs will be called in the future, i.e., identifying calling-prone higher-order functions. Our approach can assist testers to reduce the number of higher-order functions of Scala programs under test. In Phof, we extracted 24 features from source code and logs to train a predictive model based on known higher-order function calls. We empirically evaluated our approach on 4 832 higher-order functions from 27 real-world Scala projects. Experimental results show that Phof based on the random forest algorithm and the Synthetic Minority Oversampling Technique Processing strategy (SMOTE) performs well in the prediction of calls of higher-order functions. Our work can be used to support the scheduling of limited test resources.

     

时滞扰动Lorenz系统及其同步电路实现

以Lorenz系统为模型,构造一个具有多个正的Lyapunov指数的四维时滞混沌系统,分析了其基本动力学行为,并利用滤波网络技术对新系统进行了可切换电路设计.然后,基于Lyapunov方法给出了两个相同高维时滞系统的耦合同步条件,根据所提出的同步方法设计了自同步控制电路.实验表明了该时滞系统具有丰富的动力学行为,所设计的同步控制电路结构简单,易于实现,能够通过调节部分元件参数获得较好的同步性能.     

Structural analysis of neural circuits using the theory of directed graphs

A new approach to analysis of structural properties of biological neural circuits is proposed based on their representation in the form of abstract structures called directed graphs. To exemplify this methodology, structural properties of a biological neural network and randomly wired circuits (RC) were compared. The analyzed biological circuit (BC) represented a sample of 39 neural nuclei which are responsible for the control of the cardiovascular function in higher vertebrates. Initially, direct connections of both circuits were stored in a square matrix format. Then, standard algorithms derived from the theory of directed graphs were applied to analyze the pathways of the circuits according to their length (in number of synapses), degree of connectedness, and structural strength. Thus, the BC was characterized by the presence of short, reciprocal, and unidirectional pathways which presented a high degree of heterogeneity in their strengths. This heterogeneity was mainly due to the existence of a small cluster of reciprocally connected neural nuclei in the circuit that have access, through short pathways, to most of the network. On the other hand, RCs were characterized by the presence of long and mainly reciprocal pathways which showed lower and absolute homogeneous strengths. Through this study the proposed methodology was demonstrated to be a simple and efficient way to store, analyze, and compare basic neuroanatomical information.     

Higher-Order Smoothing： A Novel Semantic Smoothing Method for Text Classification

It is known that latent semantic indexing （LSI） takes advantage of implicit higher-order （or latent） structure in the association of terms and documents. Higher-order relations in LSI capture ＂latent semantics＂. These findings have inspired a novel Bayesian framework for classification named Higher-Order Naive Bayes （HONB）, which was introduced previously, that can explicitly make use of these higher-order relations. In this paper, we present a novel semantic smoothing method named Higher-Order Smoothing （HOS） for the Naive Bayes algorithm. HOS is built on a similar graph based data representation of the HONB which allows semantics in higher-order paths to be exploited. We take the concept one step further in HOS and exploit the relationships between instances of different classes. As a result, we move beyond not only instance boundaries, but also class boundaries to exploit the latent information in higher-order paths. This approach improves the parameter estimation when dealing with insufficient labeled data. Results of our extensive experiments demonstrate the value of HOS oi1 several benchmark datasets.     

高阶差分视角下的积分攻击

积分攻击和高阶差分攻击是分组密码的两种重要分析技术.尽管两者的理论基础并不相同,但是它们的攻击过程却十分相似.该文从高阶差分分析的视角来解释AES和Rijndael-256的积分区分器,证明高阶差分分析对此类算法同样有很强的分析能力.此外,改进了Rijndael-256的3轮区分器的数据复杂度.最后,给出了SPONGENT杂凑函数中间置换的14轮零和区分器.     

Combining the parabolic synthesis methodology with second-degree interpolation

The Parabolic Synthesis methodology is an approximation methodology for implementing unary functions, such as trigonometric functions, logarithms and square root, as well as binary functions, such as division, in hardware. Unary functions are extensively used in baseband for wireless/wireline communication, computer graphics, digital signal processing, robotics, astrophysics, fluid physics, games and many other areas. For high-speed applications, as well as in low-power systems, software solutions are not sufficient and a hardware implementation is therefore needed. The Parabolic Synthesis methodology is a way to implement functions in hardware based on low complexity operations that are simple to implement in hardware. A difference in the Parabolic Synthesis methodology compared to many other approximation methodologies is that it is a multiplicative, in contrast to additive, methodology. To further improve the performance of Parabolic Synthesis based designs, the methodology is combined with Second-Degree Interpolation. The paper shows that the methodology provides a significant reduction in chip area, computation delay and power consumption with preserved characteristics of the error. To evaluate this, the logarithmic function was implemented, as an example, using the Parabolic Synthesis methodology in comparison to the Parabolic Synthesis methodology combined with Second-Degree Interpolation. To further demonstrate the feasibility of both methodologies, they have been compared with the CORDIC methodology. The comparison is made on the implementation of the fractional part of the logarithmic function with a 15-bit resolution. The designs implemented using the Parabolic Synthesis methodology – with and without the Second-Degree Interpolation – perform 4x and 8x better, respectively, than the CORDIC implementation in terms of throughput. In terms of energy consumption, the CORDIC implementation consumes 140% and 800% more energy, respectively. The chip area is also smaller in the case when the Parabolic Synthesis methodology combined with Second-Degree Interpolation is used.     

Reasoning about synchronization in GALS systems

Correct design of interface circuits is crucial for the development of System-on-Chips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.     

不确定非线性系统的高阶滑模控制器设计

针对一类不确定非线性SISO系统,结合系统有限时间稳定理论与积分滑模控制理论,提出了一种新的高阶滑模控制器设计方法,改善了现有高阶滑模控制中存在的缺陷.积分滑模保证了系统初始时刻就具有抗扰能力,同时采用有限时间稳定观测器实现了高阶滑模的输出反馈控制.仿真结果表明该控制器可使系统在有限时间内收敛,并有效地减小了系统抖振.     

RTL验证中的混合可满足性求解

RTL混合可满足性求解方法分为基于可满足性模理论(SMT)和基于电路结构搜索两大类.前者主要使用逻辑推理的方法,目前已在处理器验证中得到了广泛的应用,主要得益于SMT支持用于描述验证条件的基础理论;后者能够充分地利用电路中的约束信息,因而求解效率较高.介绍了每一大类中的典型研究及其所采用的重要策略,以及RTL可满足性求解方面的研究进展.