A new assessment of the self-limiting hot-carrier degradation inLDD NMOSFET's by charge pumping measurement

By progressively lowering the gate-base level in the charge pumping (CP) measurement, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer-oxide regions, extending the interface that can be probed. This constitutes the basis of a new technique that separates the hot-carrier-induced interface states in the respective regions. Linear drain current degradation, measured at low and high gate bias, provides clear evidence that interface state generation initiates in the spacer region and progresses rapidly into the overlap/channel regions with stress time in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Experimental evidence for nonlucky electron model effect in 0.15-/spl mu/m NMOSFETs

It is shown that in 0.15-/spl mu/m NMOSFETs the device lifetime under channel hot-carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-/spl mu/m NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to increased interface state generation by the movement of the maximum impact ionization site from the lightly doped drain (LDD) diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. This paper provides experimental evidence for the non-LEM effect by comparing the degradation characteristics and the maximum impact ionization sites as a function of gate oxide thickness and gate length.     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

Simple gate-to-drain overlapped MOSFETs using poly spacers for highimmunity to channel hot-electron degradation

Short n-channel MOSFETs with permanent poly spacers over the lightly doped drain (LDD) region are demonstrated to be effective in increasing the resistance to channel hot-electron-induced degradation. The hot-electron lifetime of the poly-spacer devices is two to three orders of magnitude longer than that of a conventional oxide-spacer device. This improvement is entirely due to the reduced electron trapping in the gate oxide under the sidewall spacer. The disadvantages of the poly-spacer devices, higher gate-to-drain overlap capacitance and weaker gate oxide integrity, can both be minimized to within 20% of those of the oxide-spacer device by a short oxidation before the formation of the poly spacer     

A new LDD structure: total overlap with polysilicon spacer (TOPS)

The total overlap with polysilicon spacer (TOPS) structure, a fully overlapped lightly doped drain (LDD) structure, is discussed. The TOPS structure achieves full gate overlap of the lightly doped region with simple processing. TOPS devices have demonstrated superior performance and reliability compared to oxide-spacer LDD devices, with an order of magnitude advantage in current degradation under stress for the same initial current drive or 30% more drive for the same amount of degradation. TOPS devices also show a much smaller sensitivity to n^- dose variation than LDD devices. Gate-induced drain leakage is reported for the first time in fully overlapped LDD devices     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

A coupled study by floating-gate and charge-pumping techniques ofhot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V_d/8 to V_d) by hot-hole and/or hot-electron injections, and their generation rates (10^-9 and 10^-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I_d-V_g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I _d-V_g degradation     

应力下LDD nMOSFET栅控产生电流退化特性研究

研究了LDD nMOSFET栅控产生电流在电子和空穴交替应力下的退化特性。电子应力后栅控产生电流减小,相继的空穴注人中和之前的陷落电子而使得产生电流曲线基本恢复到初始状态。进一步发现产生电流峰值在空穴应力对电子应力引发的退化的恢复程度与阈值电压和最大饱和漏电流不同。电子应力中陷落电子位于栅漏交叠区附近的沟道侧I区和LDD侧的II区中氧化层中。GIDL应力中,空穴注入进II区中和了陷落电子,使得产生电流的退化基本得到恢复,但这些空穴并未有效中和I区中的陷落电子,因此阈值电压和最大饱和漏电流退化恢复的程度较小,分别为20%和7%。     

A new insight into the degradation behavior of the LDD N-MOSFETduring dynamic hot-carrier stressing

A new degradation behavior of LDD N-MOSFETs during dynamic hot-carrier stress is presented. Increased degradation occurs during the gate pulse transition, and involves hot-hole injection that initially begins in the oxide-spacer region, and later propagates to the channel region. Experimental results clearly show that increased degradation of the linear drain current and transconductance is mainly due to hole-induced interface traps in the oxide-spacer region. Electron trapping at hole-induced oxide defects, on the other hand, is mainly responsible for the enhanced threshold voltage shift in the late stage, when hole injection coincides with electron injection in the channel region     

A theoretical study of gate/Drain offset in LDD MOSFET's

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor, indicating the effectiveness of an LDD design in reducing the peak channel field, is used to compared LDD structures with, without, and with partial gate/drain overlap. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor (FRF) and the series resistance are presented for the three cases. Structures with gate/drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate/drain offset can cause the rise of channel field and substrate current at large gate voltages. Good agreement with simulations is obtained.     

Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

Hot carrier hardness analysis of submicrometer LDD devices

A detailed analysis of the degradation of various lightly doped drain (LDD) devices is presented. Technology parameters that are varied are gate length, LDD n-dose, and energy for devices with 20-nm gate oxide. Different DC stress conditions are investigated. To gain insight into the degradation process a simulation tool is used that self-consistently calculates the oxide damage during a DC stress experiment. This enables the location and amount of oxide charges and interface states due to hot carrier injection to be obtained. The relationship between stress-induced damage and device hot carrier hardness is discussed     

Enhanced degradation in polycrystalline silicon thin-filmtransistors under dynamic hot-carrier stress

We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G_{m max}) in static stress, G_{m max} in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation     

Hot-carrier injection suppression due to the nitride-oxide LDDspacer structure

The hot-carrier effects in silicon nitride lightly doped drain (LDD) spacer MOSFETs are discussed. It is found that the oxide thickness under the nitride film spacer affects the hot-carrier effects. The thinner the LDD spacer oxide becomes, the larger the initial drain current degradation becomes at the DC stress test and the smaller the stress time dependence becomes. After the DC stress test, reduced drain current recovers at room temperature. These phenomena are due to the large hot-carrier injection into the LDD nitride spacer, because the nitride film barrier height is much less than the silicon oxide barrier height. Therefore, it is necessary to form the LDD spacer oxide, in order to suppress the large hot-carrier injection in the nitride film LDD spacer MOSFET. The drain current shift mechanism in the nitride spacer MOSFETs is discussed, considering the lucky electron model