Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.     

The implanted zener diode (IZD) as an input protection device for MOS integrated circuits

Phosphorus implantation, performed prior to the major standard process steps in p-channel technology, is used for a well controllable reduction of the breakdown voltage of planar diodes down to values which makes them suited as protection devices. In these devices the walk-out of the breakdown voltage, which is characteristic for the field-plated types of protective devices is almost completely eliminated. The dynamic resistance of the implanted diodes can be considerably reduced by providing a second p⁺diffusion which gives rise to parasitic bipolar transistor operation during breakdown. The dynamic resistance is found to be linearly dependent on the width of the space charge layer which is ascribed to microplasma phenomena occuring during breakdown. The overvoltages against which the new devices can offer protection when used in a distributed resistance configuration of 200-µm width, are shown to be in the 10-60-kV range.     

Electrothermal characteristics of strained-Si MOSFETs in high-current operation

The electrothermal characteristics of strained-Si MOSFETs, operating in the high-current regime, have been studied using device simulation. The phonon mean-free-path of strained-Si devices in the presence of high electric fields is determined, based on fullband Monte Carlo device simulation. Strained-Si nMOS devices have higher bipolar current gain and impact ionization rates compared to bulk-Si nMOS devices due to the smaller energy bandgap and longer phonon mean-free-path. Even though strained-Si devices have self-heating problems due to the lower thermal conductivity of the buried SiGe layer, the devices can be used beneficially for electrostatic discharge protection devices to achieve lower holding voltage (V/sub h/) and higher second breakdown triggering current (I/sub t2/), compared to those of bulk-Si devices, owing to the high bipolar current gain and current uniformity.     

Impact ionization in thin silicon diodes

We study the breakdown behavior of thin, abrupt silicon pin-diodes, using a low-power optical technique which can directly measure the avalanche multiplication factors even in the presence of large tunneling currents. Our measurements agree with a simple model for nonlocal avalanche generation, and we use this model to extend the breakdown predictions to a broad class of doped diodes similar to those found in the base-collector region of bipolar devices. Based on this analysis, we make quantitative estimates for the BV/sub CEO/ breakdown of modern Si and SiGe high-speed bipolar transistors.     

Channel thickness dependence of breakdown dynamic in InP-based lattice-matched HEMTs

We have investigated, by using Monte Carlo simulations, the effects of channel thickness on the breakdown dynamics in InP-based lattice-matched HEMTs (LM-HEMTs). Breakdown is due to the parasitic bipolar action of holes generated by impact ionization and accumulated in the low electric field regions near the source. Our results show that channel shrinking results in an increase in time-to-breakdown values due to holes real-space-transfer effects occurring in thin channel devices. The breakdown behavior of thin-channel devices (channel thickness /spl les/20 nm) is dominated by the accumulation of holes in the InAlAs buffer layer; in thick-channel devices breakdown is due to the parasitic bipolar action of holes accumulating in the InGaAs channel. These results suggest a frequency dependence of breakdown which can be relevant for power rf device applications and/or in the study of device survivability to rf overstress.     

Some CMOS device constraints at low temperatures

Two of the CMOS device constraints at low temperatures have been identified, namely, the transconductance and the breakdown voltage roll-off. In the short channel devices, the transconductance first increases then decreases with the decreasing temperature. This transconductance roll-off phenomenon is likely caused by the parasitic series resistance in the source and drain regions. The breakdown voltage of the MOSFET's due to the parasitic bipolar transistor action decreases with the decreasing temperature, which is caused by the increase of the impact ionization rate at low temperatures.     

GaN_Si npn HBT特性研究

采用二维器件仿真软件对GaN/Si异质结双极晶体管进行了特性仿真研究.对GaN/Si异质结双极晶体管建立了合理准确的物理模型,包括不完全电离模型、能带模型、能带变窄模型、迁移率模型与复合模型.结果表明,GaN/Si异质结开启电压为2.5 eV.在Ib=0.2 mA时,电流放大倍数为100倍.击穿电压为900V,使其在大功率器件方面有很大应用前景.最高截止频率为100 GHz,使其可工作在射频和微波频段.     

RF small signal avalanche for bipolar transistor circuit design: Characterization, modeling and repercussions

In the face of increasing demands for high frequency and high output power of modern bipolar transistor circuits, electronic circuit designers are exploring regimes of transistor operation that meet both requirements and enter RF regimes, where impact ionization is significant. The present paper addresses AC/RF avalanche characterization techniques. Repercussions of avalanche breakdown on some important transistor properties like unilateral power gain and the stability factor are introduced and demonstrated by measurements on modern industrial devices. On the basis of theoretical considerations and compact model simulations it is shown when avalanche can be expected to have significant impact on AC performance of bipolar transistors.     

Multiple equilibrium points and their significance in the second breakdown of bipolar transistors

Suggests a simple one-dimensional model for the electrical and thermal behavior of a bipolar transistor. The proposed model can be embedded in an external circuit and analyzed by an appropriate circuit analysis program. Existence of multiple equilibrium points for certain biasing conditions is demonstrated and their implication upon the transient behavior of a device is discussed. The triggering mechanism for second breakdown in the case of forward base current, as well as reverse base current, is described in the light of these multiple equilibrium points. Prediction of that part of the safe operating area boundary limited by second breakdown is reported. The results compare favorably with the manufacturer's recommended limit.     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.     

FET circuit destruction caused by electrostatic discharge

Under certain environmental conditions, electrostatic discharges can cause catastrophic failure in both bipolar and FET integrated circuits [1]. Some devices (MOSFET's) are particularly susceptible to damage because of the relatively low destructive breakdown voltage (50 to 100 V) of their thin oxides. One source of concern is discharges from the human body during handling. This problem can be minimized by taking various approaches, such as 1) manufacturing the device so it has a high oxide breakdown voltage, 2) adding a protective device to the input, 3) developing special handling procedures to prevent high voltages from being applied to the devices accidentally. The objectives of this paper are to present a technique to test the effectiveness of FET protective devices using a simulated human static discharge and also to present a mathematical model that can predict a catastrophic failure as a function of voltage developed across the FET device and the energy dissipated. Both theoretical and experimental data are presented.     

Avalanche breakdown and surface deep-level trap effects in GaAsMESFET's

Time-dependent numerical simulations have been performed to investigate avalanche breakdown and surface deep-level trapping effects in GaAs MESFETs. The model is based on a combination of bipolar drift-diffusion transport, impact ionization, and a dynamic surface charging mechanism. A realistic trapping process is introduced into the surface trap model from which the spatial distribution of surface charge density is determined. The basic breakdown mechanisms, gate-bias-dependent breakdown voltages, and effects of surface charges are demonstrated. It is shown that the surface deep-level traps have a pronounced effect on the breakdown phenomenon     

Breakdown behavior of GaAs/AlGaAs HBTs

Avalanche breakdown behavior at the collector junction of the GaAs/AlGaAs HBT (heterojunction bipolar transistor) has been studied. Junction breakdown characteristics displaying hard breakdown, soft breakdown, and negative resistance breakdown behavior were observed and are interpreted by analysis of localized microplasma effects, uniform microplasma-free behavior, and associated current gain measurements. Light emission from the collector-base junction of the GaAs/AlGaAs HBT was observed and used to investigate breakdown uniformity. Using a simple punchthrough breakdown model, the theoretical breakdown curves at different collector doping concentrations and thicknesses were computed and found to be in agreement with maximum breakdown voltages measured from devices displaying the most uniform junction breakdown. The serious current gain degradation of GaAs/AlGaAs HBTs at low current densities was analyzed in connection with the measurement of a large collector-emitter breakdown voltage. The unexpected functional relationship between the collector-emitter breakdown voltage and collector-base breakdown voltage is explained by the absence of a hole-feedback effect for devices not exhibiting transistor action     

Interface‐Engineered Amorphous TiO2‐Based Resistive Memory Devices

Crossbar‐type bipolar resistive memory devices based on low‐temperature amorphous TiO₂ (a‐TiO₂) thin films are very promising devices for flexible nonvolatile memory applications. However, stable bipolar resistive switching from amorphous TiO₂ thin films has only been achieved for Al metal electrodes that can have severe problems like electromigration and breakdown in real applications and can be a limiting factor for novel applications like transparent electronics. Here, amorphous TiO₂‐based resistive random access memory devices are presented that universally work for any configuration of metal electrodes via engineering the top and bottom interface domains. Both by inserting an ultrathin metal layer in the top interface region and by incorporating a thin blocking layer in the bottom interface, more enhanced resistance switching and superior endurance performance can be realized. Using high‐resolution transmission electron microscopy, point energy dispersive spectroscopy, and energy‐filtering transmission electron microscopy, it is demonstrated that the stable bipolar resistive switching in metal/a‐TiO₂/metal RRAM devices is attributed to both interface domains: the top interface domain with mobile oxygen ions and the bottom interface domain for its protection against an electrical breakdown.     

Time-dependent snapback in thin-film SOI MOSFET's

During pulsed stressing of SOI MOSFETs for ESD characterization, the turn-on voltage of the parasitic bipolar transistor was observed to be a function of the stress pulse-width. This observation can be understood in terms of a capacitive charging model. The theory behind this time-dependent snapback is presented in this letter along with the experimental results. Comparisons with bulk-Si devices indicate that this phenomenon is specific to SOI and is a manifestation of the floating body effect     

Temperature dependence of avalanche multiplication in InP-based HBTs with InGaAs/InP composite collector: device characterization and physics model

Recent efforts are being focused on improving the breakdown of InP-based heterojunction bipolar transistors (HBTs) towards high-power applications. A fundamental understanding of the temperature dependence of breakdown and its physics mechanism in these devices is important. In this work, a detailed characterization of temperature-dependent collector breakdown behavior in InP DHBTs (DHBTs) with an InGaAs/InP composite collector is carried out. A physics model for the prediction of temperature-dependent breakdown in lnP/InGaAs composite collector is developed. We found that, although the variation of impact ionization coefficient due to the change of temperature may affect the device breakdown, the temperature-dependence of breakdown in the lnGaAs/InP composite collector could be significantly affected by the carrier transport in the InGaAs region. As temperature is increased, the increase in the contribution of InGaAs layer to the junction breakdown due to the reduction of electron energy relaxation length could be the root cause of the reduction of junction breakdown voltage. Good agreement between the physics model and experimental data demonstrate the validities of the proposed physics model to predict the temperature dependent breakdown characteristics for InP DHBTs.     

Analysis of fast electrothermal dynamics in power BJT

It is well known that the self heating phenomenon in power bipolar devices strongly influences the electrical behavior. Heating phenomenon is a dynamic process ruled by different time constants. While the thermal dynamics associated to external heat exchange is an order of magnitude slower than the electrical one, the thermal dynamics occurring at the silicon level near the active junction is relatively faster and can interact with the electrical one. In this paper, it is proved that such a fast thermal dynamics is responsible for unstable oscillating electrical transients that can be detected in power bipolar transistors. An electrothermal resonance phenomenon Is theoretically and experimentally verified on a commercial power BJT. It is explained how such a phenomenon ran be operatively employed to extract the parameters of the fast thermal dynamics, difficult to measure with conventional procedures     

Second breakdown—A comprehensive review

This paper is a comprehensive review of the published literature dealing with the phenomenon of second breakdown in semiconductor devices and the problems it creates in the design, fabrication, testing, and application of transistors.     

A transistor model for numerical computation of forward-biassecond-breakdown boundary

A two-dimensional bipolar power transistor model for numerical computation of the forward-bias, second-breakdown boundary is proposed. The model takes into account high-current-density effects such as the base widening (Kirk's) effect and avalanche injection. The numerically determined forward-bias safe operating area is in good agreement with the experimentally obtained area, especially at high collector currents and lower collector voltages. The model is also used to analyze the dynamics of the forward-bias second breakdown. The model is verified experimentally, and is suitable for a parametric study of forward-bias second breakdown     

三代半导体功率器件的特点与应用分析

以S i双极型功率晶体管为代表的第一代半导体功率器件和以GaAs场效应晶体管为代表的第二代半导体功率器件为雷达发射机的大规模固态化和可靠性提高做出了贡献。近年来以S iC场效应功率晶体管和GaN高电子迁移率功率晶体管为代表的第三代半导体--宽禁带半导体功率器件具有击穿电压高、功率密度高、输出功率高、工作效率高、工作频率高、瞬时带宽宽、适合在高温环境下工作和抗辐射能力强等优点。人们寄希望于宽禁带半导体功率器件来解决第一代、第二代功率器件的输出功率低、效率低和工作频率有局限性以至于无法满足现代雷达、电子对抗和通信等电子装备需求等方面的问题。文中简要介绍了半导体功率器件的发展背景、发展过程、分类、特点、应用、主要性能参数和几种常用的半导体功率器件;重点叙述了宽禁带半导体功率器件的特点、优势、研究进展和工程应用;对宽禁带半导体功率器件在新一代雷达中的应用前景和要求进行了探讨。