Threshold voltage in short-channel MOS devices

The threshold voltage in short-channel MOS transistors was investigated by use of a two-dimensional numerical solution of Poisson's equation and experimental measurements on devices of 5.15-, 3.15-, and 2.15-µm channel length. The assumption of constant equipotential surface in the oxide implicit in the charge-sharing technique is not valid in devices of shorter Channel lengths and at larger operating voltages. The numerical determination of the threshold voltage from the two-dimensional analysis agrees with experimental results. Unlike previous work, the charge-sharing model was investigated from an electric-field point of view. The inadequacies of the charge-sharing model are elucidated qualitatively and quantitatively.     

An engineering model for short-channel MOS devices

An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described. Based on a piecewise carrier drift velocity model, simplified expressions for the DC drain current I_D, the small signal transconductance g_m and the output conductance g _ds in the saturation region are derived. For a given gate voltage, the expressions depend only on the threshold voltage V _T and the dimensions of the device, whose desired values are normally known     

Operation of short-channel depletion-mode MOS devices atliquid-nitrogen temperature

Experimental observations that depletion-mode MOS devices optimized for room temperature can also work well when immersed in liquid nitrogen are reported in which the classical impurity freeze-out effect seems to vanish on short-channel devices if the drain voltage is not too small. This is attributed to field-assisted ionization mechanisms such as the Poole-Frenkel effect, with possible enhancement by self-heating. The MINIMOS 4 device simulator was modified to introduce this effect and then to check the validity of this assumption by comparison with experimental results. To prove that it is possible to take advantage of this effect a 3-bit feedback adder, used as a benchmark circuit, has been processed in an enhancement-depletion 0.5-μm NMOS technology optimized for room temperature wherein the cooling from 300 to 77 K results in an improvement from 1 to 1.3 GHz for the maximum clock frequency of operation     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Carrier transport and related phenomena in MOS devices

Silicon-based devices are currently the most attractive group because they are functioning at room temperature and can be easily integrated into conventional silicon microelectronics. There are many models and simulation programs available to compute CV curves with quantum correction [Choi C-H, Wu Y, Goo JS, Yu Z, Dutton RW. IEEE Trans on Electron Devi 2000; 47(10): 1843; Croci S, Plossu C, Burignat S. J Mater Sci Mater Electron 2003; 14: 311; Soliman L, Duval E, Benzohra M, Lheurette E, Ketata K, Ketata M. Mater Sci Semicond Process 2001; 4: 163]. This work deals with the simulation of electron transfer through SiO₂ barrier of metal–oxide–semiconductor structure (MOS). The carrier density is given by a self consistent resolution of Schrödinger and Poisson equations and then the MOS capacitance is deduced and compared with results available in literature. As it is well known, the MOS capacitance–voltage profiling provides a simple determination of structure parameters. The extracted tunnel oxide thickness and substrate doping are compared with those used in the simulation. For the purpose to investigate the electron tunnelling through the barrier, we have used the transfer matrix approach. Using I–V simulations, we have shown that the traps in SiO₂ matrix have a drastic influence on electron tunnelling through the barrier. The trap-assisted contribution to the tunnelling current is included in many models [Maserjian J, Zamani N. J Appl Phys 1982; 53(1): 559; Houssa M, Stesmans A, Heyns MM. Semicond Sci Technol 2001; 16: 427; Aziz A, Kassmi K, Kassmi Ka, Olivie F. Semicond Sci Technol 2004; 19: 877; Wu You-Lin, Lin Shi-Tin. IEEE Trans Dev Mater Reliab 2006; 6(1): 75; Larcher L. IEEE Trans Electron Dev 2003; 50(5): 1246]; this is the basis for the interpretation of stress induced leakage current (SILC) and breakdown events. Memory effect becomes typical for this structure. We have studied the I–V dependence with trap parameters.     

Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.     

On the short-channel theory for MOS transistor

An attempt is made to derive rigorous analysis for the short-channel MOS transistor on the basis of the 2-D Poisson's equation. The analysis is able to predict a correct dependence of the threshold voltage on channel length and drain voltage, avoids the need for the definition of an average depletion charge density, and gives more physical insight into the short-channel effects     

An analog system for measurement of effective surface mobility in MOS devices

A circuit consisting of several operational amplifiers and analog multiplier/dividers is used with a conductance measurement system to measure effective surface mobility of MOS devices as a function of gate voltage. Accuracy is limited to gate voltages about 1.5 V greater in magnitude than device threshold.     

A charge-based model for short-channel MOS transistor capacitances

A model that conserves charge, is valid in the strong inversion regime, and is based on the quasi-static approximation is presented. Major second-order effects such as carrier velocity saturation, mobility degradation, and channel-length modulation are included in the derivation of current and charges. The theoretical predictions of the model are compared to both experimental and numerically simulated data and are found to be in good agreement over a wide range of gate and drain voltages and to confirm many properties that have been observed or predicted     

Velocity saturation effect on short-channel MOS transistor capacitance

To analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree quite well. Several causes of short-channel effects are explained by the simulations. Velocity saturation effects are found to play a key role in the gradual increase in Cgd. Also holes in the accumulation region and the two-dimensional effect or the influence of the back-gate field from the drain are important in explaining the short-channel effect of MOS transistor capacitance.     

1/f noise in MOS devices, mobility or number fluctuations?

Recent experimental studies on 1/f noise in MOS transistors are reviewed. Arguments are given for the two schools of thought on the origin of 1/f noise. The consequences of models based on carrier-number ΔN or mobility fluctuations Δμ on the device geometry and on the bias dependence of the 1/f noise are discussed. Circuit-simulation-oriented equations for the 1/f noise are discussed. The effects of scaling down on the 1/f noise is studied in the ohmic region as well as in saturation. In the ohmic region the contribution of the series resistance often can be ignored. However, in saturation the noise of the gate-voltage-dependent series resistance on the drain side plays a role in lightly doped drain LDD mini-MOST's. Surface and bulk p-channel devices are compared and the differences between n-and p-MOST's often observed is discussed. The relation between degradation effects by hot carriers or by γ-irradiation on the one hand and the 1/f noise on the other is considered in terms of a ΔN or Δμ. Experimental results suggest that 1/f noise in n-MOST's is dominated by ΔN while in p-MOST's the noise is due to Δμ     

BSIM: Berkeley short-channel IGFET model for MOS transistors

The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.     

Electron mobility in short-channel MOSFET's with series resistances

Electron mobilities have been measured in transistors with channel lengths from 5.0 to 0.5 µm. The originally high low-field mobility µ0≈ 700 cm²/V . s seems to be greatly decreased by parasitic series resitances, to a minor degree also by surface scattering.     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

Noise in MOS bucket-brigade devices

Previous calculations of noise in bucket-brigade devices (BBD's) have ignored subthreshold leakage current even though BBD's operate in the subthreshold region over most of their useful frequency range. In this work, subthreshold leakage is included in the calculation, but surprisingly, it makes little difference in the end result. The noise spectrum in p-channel BBD's is measured and agrees well with the calculated noise spectrum which includes the effects of correlation between noise packets, imperfect charge transfer efficiency, and output circuitry.     

Moderate inversion in MOS devices

The region of validity of common approximations for weak and strong inversion is examined. It is shown that at the lower limit of what is often defined as strong inversion region, incremental quantities such as transconductance can be an order of magnitude smaller than the value predicted by using common strong inversion approximations. It is suggested that the limits of validity of widely used approximations for various quantities in weak and strong inversion can be judged by the value of a single parameter, namely the ratio of the inversion layer capacitance to the sum of the oxide capacitance and the depletion region capacitance. It is shown that in the region where this parameter takes values above 0.1, weak inversion approximations are in serious error; similarly, in the region where this parameter takes values below 10, strong inversion approximations are in serious error. The definition of a “moderate inversion region” between the above two limit points is proposed. The width of this region is calculated for a variety of process parameters and values of the quasi-Fermi potential difference, and is found to exceed 0.5 V in many cases. The accuracy of commonly used approximations for the extrapolated threshold voltage is examined.     

Two-dimensional finite element charge-sheet model of a short-channel MOS transistor

A two-dimensional charge-sheet model for short-channel MOS transistors has been developed. The unique feature of the model is that the effect of channel inversion layer charge is included as a nonlinear integral boundary condition on the two-dimensional electrostatic field in the transistor. The average inversion layer charge density and source-drain current are obtained directly from the model rather than from the electron density or electron quasi-Fermi level. The model retains all of the physical detail of more complex two-dimensional models such as sensitivity to source-drain profile shape, channel profile, and oxide field shape. This allows the model to represent the changes in drain current associated with short-channel effects while still allowing simple comparison with long-channel models. For long-channel transistors, the results of this model are identical to Brews' long-channel charge-sheet model. The accuracy of this model is verified by modeling a sequence of transistors with channel lengths between 4.6 and 1.1 μm. In short-channel transistors, effects previously attributed to high field mobility are explained by simple two-dimensional electrostatics.The simulations produced using this model have been compared to experimental measurements on an array of n-channel MOSFETs; the model is in good agreement for transistors with channel lengths as short as 1.1 μm. In this verification process, the model represented accurately the onset of subthreshold current, channel-length-induced threshold voltage offset, and drain-field-induced output conductance changes.From studies of numerical accuracy, we conclude that the charge-sheet model can easily simulate drain current with an accuracy which exceeds that required for most applications. To obtain 5% accuracy for drain current, a 146 element mesh is sufficient. Refinement of the 146 element mesh to a 455 element mesh gives a current which is accurate to 0.16%. Average computer time for a high current solution is 2.5 min on a DEC-20.The numerical solutions were obtained using general-purpose software for solving elliptic partial differential equations. We have been able to solve problems with exact solutions to test the correctness and accuracy of our codes. We also can easily change the physics included in our model and the geometry of the transistor. The finite element method used allows refinement of oblique triangles which is important in achieving computational efficiency. The program is portable and has been run on a DEC-20, a VAX $\text{11}\text{780}$, a Cyber 175 and a Univac 1108.