A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I _s , threshold voltage V _T0, gamma γ, θ _o (dependent on mobility degradation and source-drain series resistances), and θ _e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23–61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.     

Input-Free V TP and - V TN Extractor Circuits Realized on the Same Chip

The paper describes a self-biased CMOS transistor circuit with two outputs providing the transistor threshold voltages, V _TP and -V _TN . Both outputs are referenced to the same V _DD supply line, and hence, the circuit can be used as a convenient test device. The V _TP extractor is based on the nested connection of two transistors; the -V _TN extractor is designed using the difference of gate-source voltages in two different size transistors carrying equal currents. The circuit was realized in 0.8 m technology, and the results of simulation and experiment are compared. Recommendations to improve the design are given.     

600V HVIC高噪声抑制电平移位电路

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block’s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.     

A Very High-Frequency Transistor-Only Linear Tunable Companding Current-Mode Integrator

A low-distortion tunable transistor-only integrator suitable for applications in the frequency range approaching the f _T of transistors is presented. The circuit is a modified version of the recently introduced companding current-mode integrator utilizing the non-linear base-emitter diffusion capacitance of the BJT. A first-order approximation of the circuit characteristics is explained, followed by a brief discussion on the departure from ideal characteristics due to transistor nonidealities. Experimental and simulated results of practical integrators are given to verify the feasibility of the proposed modified circuit.     

Synthesis of Ultrathin,Homogeneous Copolymer Dielectrics to Control the Threshold Voltage of Organic Thin‐Film Transistors

This work demonstrates that threshold voltage (V_T) of organic thin‐film transistors (OTFTs) can be controlled systematically by introducing new copolymer dielectrics with electropositive functionality. A series of homogeneous copolymer dielectrics are polymerized from two monomers, 1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane (V3D3) and 1‐vinylimidazole (VI), via initiated chemical vapor deposition. The chemical composition of the copolymer dielectrics is exquisitely controlled to tune the V_T of C₆₀ OTFTs. In particular, all the copolymer dielectrics demonstrated in this work exhibit extremely low leakage current densities (lower than 2.5 × 10^?8 A cm^?2 at ±3 MV cm^?1) even with a thickness less than 23 nm. Furthermore, by introducing an ultrathin pV3D3 interfacial layer (about 3 nm) between the copolymer dielectrics and C₆₀ semiconductor, the high mobility of the C₆₀ OTFTs (about 1 cm² V^?1 s^?1) remains unperturbed, showing that V_T can be controlled independently by tuning the composition of the copolymer dielectrics. Coupled with the ultralow dielectric thickness, the independent V_T controllability allows the V_T to be aligned near 0 V with sub‐3 V operating voltage, which enables a substantial decrease of device power consumption. The suggested method can be employed widely to enhance device performance and reduce power consumption in various organic integrated circuit applications.     

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V _th = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V _th = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.     

Single‐Electron Pass‐Transistor Logic with Multiple Tunnel Junctions and Its Hybrid Circuit with MOSFETs

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single‐electron pass‐transistor logic circuit employing a multiple‐tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single‐electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3‐MTJ inverter circuit is simulated at 15 K with parameters C_g=C_T=C_clk=1 aF, R_T=5 MΩ, V_clk=40 mV, and V_in=20 mV. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ‐SETD logic is successfully translated to the voltage state logic.     

An alternative to source degeneration of CMOS differential pair

This paper presents a method to extend linear range of conventional CMOS source-coupled pair with transistor polarised on saturation of strong inversion. The used principle is similar to the principle of source degeneration, but the additional device is horizontally added, in parallel with the input transistors, which overcame the constraints on common mode range and supply voltage and allow low voltage operation. SPICE simulations using 0.35 μm CMOS process and a bias current of 10 μA, show that for less than 1% of transconductance variation, the linear range is up to 0.35 V _pp in comparison to 0.1 V _pp for source-degenerated pair, and 0.01 V _pp for conventional differential pair, under the same biasing current and geometrical dimensions.     

An improved and simple parameter extraction method and scaling model for RF MOSFETs up to 40 GHz

In this article, a simple and efficient extraction procedure for the extrinsic gate, drain and source resistances is presented. The substrate network parameter, C _sub, dependent on the drain–source (V _ds) voltage is extracted in transistor cut-off region. The scaling rules of the extrinsic and intrinsic parameters are given in detail. Good agreement is obtained between the simulated and measured results for the 0.13?µm radio frequency metal oxide semiconductor field effect transistors in the frequency range of 0.1–40?GHz.     

Lateral Injection Utilized for Improving the Performance of Microwave Bipolar Transistors

An experimental evaluation is presented concerning the common-emitter parameters and output current–voltage characteristics of chip n–p–n transistors that are designed for pulsed conditions and have gain–bandwidth products, f _T, higher than 300 MHz. The configuration of the emitter and collector junctions essentially embodies a new concept whereby injection efficiency is increased by lateral injection. It is shown that the new approach enables one to improve transistor performance. Some process techniques for the transistors are described.     

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

A simple division circuit

The design of a simple circuit, which can divide one voltage V₂ by another V V₁, is described. The circuit employs two operational amplifiers, a comparator and a programmable unijunction transistor (PUT). The output V V₀ is in the form V₀ = K( V V₂/ V V₁). where K is a constant which can be programmed through the PUT.     

A new multitime programmable non-volatile memory cell using high voltage NMOS

A new multitime programmable (MTP) non-volatile memory (NVM) cell using high voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high voltage NMOS is used for selecting the memory cell. The memory cell has fewer number of transistors and terminals compared with the typical conventional memory cell. This reduces the area consumption and simplifies the implementation of memory's external circuit. In addition, the subthreshold swing (SS) of the memory cell is improved for larger coupling ratio. Experimental investigation on transfer characteristics, endurance, retention, and threshold voltage V_TH shift and leakage current of the high voltage NMOS of the memory cell are presented. The experimental endurance behaviour of the proposed memory cell is superior to the conventional memory cell.     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, V_T shift due to Hot Carrier Injection stress is accelerated on small width devices. V_T matching is also degraded during stress as a function of V_T deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.     

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dV_th/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dV_th/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dV_th/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (Φ_TiN) and its temperature coefficient (dΦ_TiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).     

Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics

A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO₂ nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the I–V curve, a threshold voltage (V_T) of 2.2 V, a field-effect mobility on the order of 0.1 cm²/V s and an I_ON/I_OFF ratio of about 10⁴. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.     

Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.