Electrical characteristics of low temperature-Al0.3Ga0.7As

In this work, we present electrical characterizations of n⁺ GaAs/low temperature (LT)-Al_0.3Ga_0.7As/n⁺ GaAs resistor structures in which the LT layers are grown at nominal substrate temperatures of 250 and 300°C. The resistivity and V_tfl parameters of these LT-Al_0.3Ga_0.7As layers are compared with those of LT-GaAs and Al_0.3Ga_0.7As grown at a normal growth temperature of 720°C. Low-temperature Al_0.3Ga_0.7As layers exhibit resistivities as high as 10¹² ohm-cm, nearly four orders of magnitude higher than that of LT-GaAs, and V_tfl values as high as 45 V, over twice that of LT-GaAs. We also find that the LT-Al_0.3Ga_0.7As materials grown at 250 and 300°C appear to show opposite and contradictory trends with respect to resistivity and V_tfl. We propose that this result can be explained by residual hopping conduction in the 250°C material. Temperature dependent conductivity measurements confirm the presence of a hopping mechanism in LT-Al_0.3Ga_0.7As grown at 250°C and yield activation energies of 0.77 and 0.95 eV for LT-GaAs and LT-Al_0.3Ga_0.7As, respectively.     

Thermal stability of MISFET with low-temp molecular-beamepitaxy-grown GaAs and Al0.3Ga0.7As gate ins

GaAs and Al_0.3Ga_0.7As epilayers grown at LT by MBE were used as insulators in the fabrication of MISFET devices. Parametric changes were used to evaluate the thermal stability of MISFET, to identify failure mechanisms and validate the reliability of these devices. The LT-Al_0.3Ga_0.7As MISFET showed superior thermal stability. The degradation in the performance of MISFET with 1000 Å thick LT-GaAs gate insulator was worse than those of the MESFET. On the other hand, MISFET with 250 Å thick LT-GaAs gate insulators exhibited stable characteristics with thermal stressing, LF (low frequency) noise studies on the TLM structures of MISFET layers exhibited 1/f noise in the LT-Al_0.3Ga_0.7As samples and 250 Å LT-GaAs samples; whereas the 1000 Å thick LT-GaAs samples exhibited 1/f^3/2 noise, which was attributed to: (i) the thermal noise generated at the interface of the insulator, and (ii) the active layer due to the outdiffused metallic arsenic. Reverse gate-drain current degradation experiments were carried out at 120°C, 160°C, 200°C, and 240°C. Transconductance frequency dispersion studies were carried out before and after thermal stress on these MISFET. The transconductance of MISFET with 1000 Å LT-GaAs gate insulators was degraded by 40% at 100 kHz after thermal stress. The rest of the samples exhibited stable characteristics. These results indicate that composition changes had occurred at the interface in thicker LT-GaAs MISFET structures. Thinner LT-layers are ideal for achieving higher transconductance and better thermal stability without sacrificing the power capability of MISFET     

Germanium as a deep level in alxga1− xas grown by organometallic vapor phase epitaxy

Optoelectronic devices require materials which exhibit extremely low trap concentrations. The Al_xGa_1−xAs system has been used extensively for optoelectronic applications despite trap concentrations in the Al_xGa_1−xAs which limit the efficiency of the resulting devices. Deep level transient spectroscopy (DLTS) performed on Al_0.2Ga_0.8As layers grown by organometallic vapor phase epitaxy (OMVPE) has revealed three traps with concentrations >10¹³ cm⁻³ -E _c-E_t = 0.3, 0.5 and 0.7 eV. The dominant source of the 0.3 eV trap has proven to be a Ge impurity in arsine. SIMS analysis of Al_0.2Ga_0.8As samples show Ge as the only candidate for the impurity responsible for the 0.3 eV trap. DLTS and SIMS analysis performed on Al_0.2Ga_0.8As samples intentionally doped with Ge displayed a proportional increase in the 0.3 eV trap concentration with the Ge concentration and establishes that Ge is indeed the source of the 0.3 eV trap in Al_xGa_1−xAs. Comparison of C-V, SIMS and DLTS measurements performed on Al_xGa_1-xAs:Ge indicate that approximately 30% of elemental Ge incorporated created the 0.3 eV trap, DX_Ge.     

Annealing of AsGa-related defects in LT-GaAs: The role of gallium vacancies

We have studied the annealing properties of As_Ga-related defects in layers of GaAs grown at low substrate temperatures (300°C) by molecular beam epitaxy (low temperature[LTx]-GaAs). The concentration of neutral As_Ga-related native defects, estimated by infrared absorption measurements, ranges from 2×10¹⁹ to 1×10²⁰ cm⁻³. Slow positron annihilation results indicate an excess concentration of Ga vacancies in LT layers over bulk grown crystals. A sharp annealing stage at 450°C marks a rapid decrease in the As_Ga defect concentration. We propose that the defect removal mechanism is the diffusion of As_Ga to arsenic precipitates, which is enhanced by the presence of excess V_Ga. The supersaturated concentration of V_Ga must also decrease. Hence, the diffusivity of the As_Ga defects is time dependent. Analysis of isothermal annealing kinetics gives an enthalpy of migration of 2.0±0.3 eV for the photoquenchable As_Ga defects, 1.5±0.3 eV for the V_Ga, and 1.1±0.3 eV for the nonphotoquenchable defects. The difference in activation enthalpy represents difference energy between an As atom and Ga atom swapping sites with a V_Ga.     

Capacitance study of electron traps in low-temperature-grown GaAs

Electron traps in GaAs grown by MBE at temperatures of 200–300°C (LT-GaAs) were studied. Capacitance deep level transient spectroscopy (DLTS) was used to study the Schottky barrier on n-GaAs, whose space-charge region contained a built-in LT-GaAs layer ∼0.1 μm thick. The size of arsenic clusters formed in LT-GaAs on annealing at 580°C depended on the growth temperature. Two new types of electron traps were found in LT-GaAs layers grown at 200°C and containing As clusters 6–8 nm in diameter. The activation energy of thermal electron emission from these traps was 0.47 and 0.59 eV, and their concentration was ∼10¹⁷ cm⁻³, which is comparable with the concentration of As clusters determined by transmission electron microscopy. In LT-GaAs samples that were grown at 300°C and contained no arsenic clusters, the activation energy of traps was 0.61 eV. The interrelation between these electron levels and the system of As clusters and point defects in LT-GaAs is discussed. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 38, No. 4, 2004, pp. 401–406. Original Russian Text Copyright ? 2004 by Brunkov, Gutkin, Moiseenko, Musikhin, Chaldyshev, Cherkashin, Konnikov, Preobrazhenskii, Putyato, Semyagin.     

Interface trap and interface depletion in lattice-mismatched GaInAs/GaAs heterostructures

The effects of lattice mismatch on the deep traps and interface depletion have been studied for the Ga_0.92In_0.08As(p⁺)/GaAs(N) and Ga_0.92In_0.08As(n)/GaAs(SI) heterostructures grown by molecular beam epitaxy. We have used deep level transient spectroscopy (DLTS) and admittance spectroscopy (AS) and observed two hole traps, one at an energy ranging from 0.1 to 0.4 eV and the other at 0.64 eV, and two electron traps at 0.49 and 0.83 eV in the GalnAs/GaAsp ⁺-N junction sample. The hole trap appeared as a broad peak in the DLTS data and its energy distribution (0.1 ∼ 0.4 eV) was obtained by a simulation fitting of the peak. Concentration of this distributed hole trap increased as the in-plane mismatch increased, suggesting its relation to defects induced by lattice relaxation, whereas the other traps are from the bulk. The misfit dislocations are believed to be responsible for the interface trap. For the Ga_0.92In_0.08As(n)/GaAs(SI) samples, Hall effect measurements showed an increased interface depletion width of about 0.14 Μm for the 0.5 Μm thick layer and about 0.12 /gmm for the 0.25 Μm thick layer, while a corresponding GaAs/GaAs sample had only 0.088 Μm for the interface depletion width.     

Capacitance–conductance–current–voltage characteristics of atomic layer deposited Au/Ti/Al2O3/n-GaAs MIS structures

We have studied the admittance and current–voltage characteristics of the Au/Ti/Al₂O₃/n-GaAs structure. The Al₂O₃ layer of about 5 nm was formed on the n-GaAs by atomic layer deposition. The barrier height (BH) and ideality factor values of 1.18 eV and 2.45 were obtained from the forward-bias ln I vs V plot at 300 K. The BH value of 1.18 eV is larger than the values reported for conventional Ti/n-GaAs or Au/Ti/n-GaAs diodes. The barrier modification is very important in metal semiconductor devices. The use of an increased barrier diode as the gate can provide an adequate barrier height for FET operation while the decreased barrier diodes also show promise as small signal zero-bias rectifiers and microwave. The experimental capacitance and conductance characteristics were corrected by taking into account the device series resistance R_s. It has been seen that the non-correction characteristics cause a serious error in the extraction of the interfacial properties. Furthermore, the device behaved more capacitive at the reverse bias voltage range rather than the forward bias voltage range because the phase angle in the reverse bias has remained unchanged as 90° independent of the measurement frequency.     

Al0.3Ga0.7As-GaAs microwave resonant tunneling oscillator

We describe the design of a microwave oscillator using resonant tunneling diodes. The devices are fabricated from Al_0.3Ga_0.7As-GaAs double barrier hetero-structures grown by molecular beam epitaxy. Design criteria improving current drivability are established from a theoretical study of tunneling transmission probabilities. Very high peak current densities up to 3.10⁴ A/cm², favorable for high frequency operation as an oscillator, have been achieved experimentally. The devices exhibit stable oscillations at liquid nitrogen temperature and at room temperature when the tunnel diode oscillator is constructed with a stabilizing network.     

The formation of elevated barrier height Schottky diodes to inp and In0.53Ga0.47as using thin,excimer laser-deposited Cd interlayers

Much recent attention has been paid to elevating the barrier height of contacts to InP and In_0.53Ga_{0. 47}As via the formation of a thin, intermediate layer between the semicon-ductor and a conventionally deposited, highly conductive contact layer. Here, we report on the use of thin (～200Å) excimer laser photodeposited Cd as an interlayer between these semiconductors and Au overlayers in order to raise the barrier height of the re-sulting diodes. Current-voltage measurements of ideal Schottky diodes fabricated using this process yield barrier heights of 0.70 eV and 0.55 eV to InP and In_0.53Ga_{0. 47}As, re-spectively. The photodeposition process has been integrated with conventional clean room processing resulting in Au/Cd/In_0.53Ga_{0. 47}As transistors with high transconductances (～200 mS/mm) and operating frequencies (f _max ～ 30 GHz). X-ray photoelectron spec-troscopy of thin Cd photodeposits on InP shows that the process produces an interfacial (～10Å thick) Cd-InP reaction zone covered by metallic Cd.     

Study of grown-in defects and effect of thermal annealing in Al0.3Ga0.7As and GaAs LPE layers

Studies of the grown-in deep-level defects in the undoped n-Al_xGa_1-xAs (x = 0.3) and GaAs epitaxial layers prepared by the liquid phase epitaxy (LPE) techniques have been made, using DLTS, I-V and C-V measurements. The effect of 300 °C thermal annealing on the grown-in defects was investigated as a function of annealing time. The results showed that significant reduction in these grown-in defects can be achieved via low temperature thermal annealing process. The main electron and hole traps observed in the Al_0.3Ga_0.7As LPE layer were due to the E_c-0.31 eV and E_v+0.18 eV level, respectively, while for the GaAs LPE layer, the electron traps were due to the E_c-0.42 and 0.60 eV levels, and the hole traps were due to E_v+0.40 and 0.71 eV levels. Research supported in part by the Air Force Wright Aeronautical Laboratories, Aeropropulsion Lab., Wright Patterson Air Force Base, Ohio, subcontract through SCEEE, contract F33615-81-C-2011, task-4, and in part by AFOSR grant no. 81-0187.     

High performance AlAs/GaXIn1-xAs resonant tunneling diodes by metalorganic chemical vapor deposition

We report on AlAs/Ga_xJn_1−xAs (x = 0.47) quantum well heterostructures grown by metalorganic chemical vapor deposition (MOCVD) on InP substrates. Heterostructure quality was evaluated by high resolution x-ray diffraction for various growth conditions. Double barrier quantum well heterostructures were grown and processed into resonant tunneling diodes (RTDs). Room temperature electrical measurements of the RTDs yielded maximum peak to valley current ratios of 7.7 with peak current density of 96 kA/cm² and 11.3 with peak current density of 12 kA/cm², for devices grown by atmospheric and low pressure MOCVD, respectively.     

Nonequilibrium room-temperature carrier distribution in InAs quantum dots overgrown with thin AlAs/InAlAs layers

The optical properties of quantum dots (QDs) formed in GaAs or Al_0.3Ga_0.7As matrices by overgrowth of initial InAs islands formed in the Stranski-Krastanov mode with thin AlAs/InAlAs layers have been studied. It is shown that no transport of carriers between the QDs occurs in the temperature range 10–300 K, so the carrier distribution is of a nonequilibrium nature. The thermal excitation of carriers from the QDs is suppressed by an increase in the energy spacing between the ground and excited states, absence of the level related to the wetting layer, and higher carrier localization energy in the QDs with respect to the continuum states when the Al_0.3Ga_0.7As matrix is used.     

Al x Ga1 – x As/GaAs/Al x Ga1 – x As Double Quantum Well with a Thin AlAs Interwell Barrier: Structural Characterization by SIMS and XRD

An Al _x Ga_{1 – x} As/GaAs/Al _x Ga_{1 – x} As double quantum well with a thin AlAs interwell barrier is examined by SIMS and double-crystal XRD for an AlAs thickness of about 10 or 18 Å. Thickness and other structural parameters are determined for each layer. The rocking curves are found to indicate a fairly abrupt interwell barrier.     

Effect of Se-doping on deep impurities in AlxGa1−xAs grown by metalorganic chemical vapor deposition

We have studied the effect of Se-doping on deep impurities in Al_xGa_1−xAs (x = 0.2∼0.3) grown by metalorganic chemical vapor deposition (MOCVD). Deep impurities in various Se-doped Al_xGa_1−xAs layers grown on GaAs substrates were measured by deep level transient spectroscopy and secondary ion mass spectroscopy. We have found that the commonly observed oxygen contamination-related deep levels at E_c-0.53 and 0.70 eV and germanium-related level at E_c-0.30 eV in MOCVD grown Al_xGa_1−xAs can be effectively eliminated by Se-doping. In addition, a deep hole level located at E_y + 0.65 eV was found for the first time in Se-doped Al_xGa_1-xAs when Se ≥2 × 10¹⁷ cm⁻³ or x ≥ 0.25. The concentration of this hole trap increases with increasing Se doping level and Al composition. Under optimized Se-doping conditions, an extremely low deep level density (N_t less than 5 × 10¹² cm⁻³, detection limit) Al_0.22Ga_0.78As layer was achieved. A p-type Al_0.2Ga_0.8As layer with a low deep level density was also obtained by a (Zn, Se) codoping technique.     

Hall and photoluminescence studies of effects of the thickness of an additional In0.3Ga0.7As layer in the center of In0.15Ga0.85As/Al0.25Ga0.75As/GaAs high electron mobility transistors

In order to reduce the noise and carrier–donor scattering and thereby increase the carrier mobility of the pseudomorphic AlGaAs/InGaAs high electron mobility transistors (pHEMTs), we have grown Al_0.25Ga_0.75As/In_0.15Ga_0.85As/In_0.3Ga_0.7As/GaAs pHEMTs with varied In_0.3Ga_0.7As thickness, and studied the effects of the In_0.3Ga_0.7As thickness on the electron mobility and sheet density by Hall measurements and photoluminescence measurements. We calculated the electron and hole subbands and obtained good agreement between calculated and measured PL energies. It was found that the additional In_0.3Ga_0.7As layer could be used to reduce the carrier–donor scattering, but due to the increased interface roughness as the In_0.3Ga_0.7As layer becomes thicker, the interface scattering reduced the electron mobility. An optimal thickness of the In_0.3Ga_0.7As was found to be 2 nm.     

Characteristics of Si3N4/GaAs metal-lnsulator-semiconductor interfaces with coherent Si/Al0.3Ga0.7As interlayers

Si₃N₄/GaAs metal-insulator-semiconductor (MIS) interfaces with Si(10Å)/ Al_0.3Ga_0.7As (20Å) interface control layers have been characterized using capacitance-voltage (C-V) and conductance methods. The structure was in situ grown by a combination of molecular beam epitaxy and chemical vapor deposition. A density of interface states in the 1.1 × 10¹¹ eV^-1 cm^-2 range near the GaAs midgap as determined by the conductance loss has been attained with an ex situ solid phase annealing of 600°C in N₂ ambient. A dip quasi-static C-V demonstrating the inversion of the minority-carrier verifies the decent interface quality of GaAs MIS interface. The hysteresis and frequency dispersion of the MIS capacitors were lower than 100 mV, some of them as low as 50 mV under a field swing of about ±2 MV/cm. The increase of the conductance loss at higher frequencies was observed when employing the surface potential toward conduction band edge, suggesting the dominance of faster traps. Self-aligned gate depletion mode GaAs metal-insulator-semiconductor field-effect transistors with Si/Al_0.3Ga_0.7As interlayers having 3 μm gate lengths exhibited a transconductance of about 114 mS/mm. The present article reports the first application of pseudomorphic Si/ Al_0.3Ga_0.7As interlayers to ideal GaAs MIS devices and demonstrates a favorable interface stability.     

Diffusion of zinc into gaas through Al0.3Ga00.7As

The diffusion of zinc into GaAs, Al_0.3Ga_0.7As and Al_0.3Ga_0.7As/GaAs single heterostructures have been studied. The depth of the diffusion front is found to be proportional to the square root of the diffusion time, [t]^1/2, and for single heterostructures the Al_0.3Ga_0.7As layer thickness,d ₁ modifies this relationship through decreasing the junction depth byd ₁ multiplied by a constant. It is shown that this relationship can be used for predicting diffusion fronts in double heterostructures.     

Photoluminescence study of AlGaAs/GaAs/AlGaAs double quantum wells separated by a thin AlAs layer

Photoluminescence (PL) spectra of Al_0.21Ga_0.79As/GaAs/Al_0.21Ga_0.79As double quantum wells (DQWs) separated by a thin AlAs barrier have been studied in the temperature range 77–300 K. The well width was varied from 65 to 175 Å, and the thickness of the AlAs barrier was 5, 10, or 20 Å. In the case of a sufficiently thin (5, 10 Å) AlAs barrier, the energy spectrum of QW states is considerably modified by coupling between the QWs. This effect shifts the main spectral peak of PL, and specific features associated with the splitting of the ground state into symmetric and asymmetric states are observed in the spectra at higher temperatures. The DQW structure with a 20-Å-thick AlAs barrier is a system of two uncoupled asymmetric Al_0.21Ga_0.79As/GaAs/AlAs QWs. The energy levels in double coupled QWs were calculated as functions of the well width and AlAs barrier thickness, and good correlation with the experimentally observed energies of optical transitions was obtained.     

The effect of strained Al0.7In0.3As emitter layers on abrupt N-p+ AllnAs-GaInAs heterojunction diodes and heterojunction bipolar transistors

Strained Al_xIn_1−xAs/Ga_0.47In_0.53As heterojunction N-p⁺ diodes and heterojunction bipolar transistors (HBTs) have been grown on InP substrates by solid-source molecular-beam epitaxy, fabricated, and characterized. To determine the effects of the conduction-band discontinuity at the emitter-base heterojunction on turn-on voltage and ideality factor, a strained Al_0.7In_0.3As layer is inserted in the emitter near the base. Changes in transport across the junction are observed as a function of the strained-layer position and thickness. These results were used to implement strained emitter HBTs.     

Study of electrically active defects in n-GaN layer

Deep level defects in both p⁺/n junctions and n-type Schottky GaN diodes are studied using the Fourier transform deep level transient spectroscopy. An electron trap level was detected in the range of energies at E_c−E_t=0.23–0.27 eV with a capture cross-section of the order of 10⁻¹⁹–10⁻¹⁶ cm² for both the p⁺/n and n-type Schottky GaN diodes. For one set of p⁺/n diodes with a structure of Au/Pt/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au and the n-type Schottky diodes, two other common electron traps are found at energy positions, E_c−E_t=0.53–0.56 eV and 0.79–0.82 eV. In addition, an electron trap level with energy position at E_c−E_t=1.07 eV and a capture cross-section of σ_n=1.6×10⁻¹³ cm² are detected for the n-type Schottky diodes. This trap level has not been previously reported in the literature. For the other set of p⁺/n diodes with a structure of Au/Ni/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au, a prominent minority carrier (hole) trap level was also identified with an energy position at E_t−E_v=0.85 eV and a capture cross-section of σ_n=8.1×10⁻¹⁴ cm². The 0.56 eV electron trap level observed in n-type Schottky diode and the 0.23 eV electron trap level detected in the p⁺/n diode with Ni/Au contact are attributed to the extended defects based on the observation of logarithmic capture kinetics.