Enhancement-Mode n-Channel GaN MOSFETs on p and n-GaN/Sapphire Substrates

We report on the demonstration of enhancement-mode n-channel GaN high-voltage MOSFET realized on both p and$hboxn^-$GaN epilayer on sapphire substrates. These MOSFETs, with linear and circular gate geometries, show good dc characteristics with maximum field-effect mobility of 167$hboxcm^2/hboxV cdot hboxs$, best reported to date.     

High-Speed Enhancement-Mode GaAs MESFET Logic

High-speed enhancement-mode GaAs MESFET Iogic circuits have been fabricated by electron beam lithography. A 15-stage ring oscillator composed of 0.8-mu m gatelength and 40-mu m gatewidth inverters has given a minimum propagation delay time of 77 ps at a power dissipation of 977 mu W. A minimum power-delay product of 1.6 fJ has been obtained with a 20-mu m gatewidth circuit at a propagation delay time of 200 ps. Liquid nitrogen temperature operation has also been performed, and a speed almost twice higher than that at room temperature has been obtained. The minimum propagation delay time was 51 ps, and the associated power dissipation was 1.9 mW.     

GaAs MOSFET High-Speed Logic

Enhancement-mode GaAs MOSFET integrated logic shows superior potential for applications in low-power high-speed integrated circuits. The speed / power performance of this logic was investigated by using GaAs MOSFET ring oscillators, fabricated using a low-temperature plasma oxidation technique for gate insulation. With an enhancement-depletion (E/D)-type ring oscillator, a minimum propagation delay of 110 ps per gate is obtained, with a power/speed product of 2.0 pJ. With an enhancement-enhancement (E/E) type, a minimum power/speed product of 26 fJ is obtained, with a 385-ps delay. These performances are equal to or better than those of GaAs MESFET logic, after adjustments are made for gate size. With further refinements in device geometry and improvements in gate oxide, GaAs MOSFET logic will be of great use in high-speed very-large-scale integrated circuits.     

Double-Epilayer Structure for Low Drain Voltage Rating n-Channel Power Trench MOSFET Devices

Double-epilayer structures were studied for n-channel low-voltage power trench MOSFET devices with drain-to-source voltage (V_ds) of 20 V, and various device performance improvements have been observed. The threshold voltage variation (sigma_Vth) can be reduced by increasing the intrinsic epilayer thickness. A 9% effective electron mobility mu_n improvement has been observed and is attributed to the reduced background phosphorus scattering. A Q_gd of 3.1 nC for double- epilayer structure is observed which is about 30% lower than the 4.5 nC for the single-epilayer structure. This improved Qgd is due to both an increasing depletion width at the bottom of the trench and the well junction moving toward the trench bottom for the double-epilayer structure. The dependence of Qgd on the double-epilayer structure (intrinsic epilayer thickness and the doped epilayer resistivity) is found following the power law Q_gd prop alphaX^-b, where a and b are double-epilayer structure dependent. Compared to the single-epilayer structure, a double- epilayer structure can handle larger reverse current, suggesting a smaller basis resistance (R_bb') for the double-epilayer structure. This improvement ranges from 7% to 24% depending on the die pitch. A 20% less temperature dependence of device on-resistance for the double-epilayer structure has also been observed. This enables a large forward current capability, although the mechanism is not well understood.     

Planar GaAs MOSFET integrated logic

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.     

Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD$hboxHfO_2$has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation.     

GaAs enhancement/depletion n-channel MOSFET

The state of the art in the development of GaAs n-channel enhancement/depletion MOSFETs is presented. The static, non-equilibrium and dynamic characteristics are discussed and compared with the behaviour of large-area MOS diodes and a simple theory. It can be concluded, that the device is basically feasible for high speed logic enhancement circuits, pulse recovery purposes and for power applications, although some major oxide/semiconductor interface problems have still to be sorted out.     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

Screening of Oxide/GaAs Interfaces for MOSFET Applications

Photoluminescence intensity (PL-I) data are presented for 22 dielectric/GaAs systems investigated for MOSFET applications. The PL-I technique has been identified as a most useful and reliable tool for screening dielectric/GaAs interfaces and has been instrumental in the identification of a device quality dielectric/GaAs interface: in situ deposited $ hbox{Ga}_{2}hbox{O}_{3}$ on GaAs. The early discovery of such an interface has allowed us to focus resources and to succeed to manufacture GaAs MOSFETs which perform in line with theoretical model predictions after more than 40 years of failed attempts. It is strongly recommended to extend the technique to the investigation of CMOS relevant channel materials such as InGaAs.      

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

Microwave performance of GaAs MOSFET with wet thermally oxidized InAlP gate dielectric

This paper reports the first demonstration of a microwave-frequency operation of a GaAs MOSFET fabricated using a wet thermal oxidization of InAlP lattice-matched to GaAs to form a native-oxide gate insulator. Devices with 1-/spl mu/m gate lengths exhibit a cutoff frequency (f/sub t/) of 13.7 GHz and a maximum frequency of oscillation (f/sub max/) of 37.6 GHz, as well as a peak extrinsic transconductance of 73.6 mS/mm. A low-leakage current density of 3.8/spl times/10/sup -3/ A/cm/sup 2/ at 1-V bias for an MOS capacitor demonstrates the good insulating properties of the /spl sim/ 11-nm thick native gate oxide.     

Improved enhancement/depletion GaAs MOSFET using anodic oxide as the gate insulator

A GaAs MOSFET with a semi-insulating substrate is described, operating in either the enhancement or the deed depletion modes and showing the highest transconductance reported so far, and a rise time better than 1 ns. The behavior is fully explained by theC/Vcharacteristics of equivalent MOS capacitors.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Comments on “High Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm”

We have a number of issues with the above paper ldquoHigh Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Current Exceeding 1 A/mm,rdquo by Y. Xuan, Y. Q. Wu, and P. D. Ye, published IEEE Electron Device Letters in April 2008 which we wish to highlight.     

A nanoanalytical investigation of high-k dielectric gate stacks for GaAs based MOSFET devices

In this paper a quantitative determination of the elemental distributions across a ∼10 nm Ga₂O₃/GdGaO layer with a Pt metal gate cap on top of an InGaAs/AlGaAs/GaAs substrate is presented. Some effects of annealing on the elemental distribution across the Ga₂O₃/GdGaO oxide layer are described. The paper also discusses the analysis of the interface GaAs/Ga₂O₃/GGO at a sub-nm level by high-resolution HAADF STEM imaging.     

Fabrication of depletion-mode GaAs MOSFET with a selectiveoxidation process by using metal as the mask

The n-channel depletion-mode GaAs MOSFETs with a selective liquid phase chemical-enhanced oxidation method at low temperature by using metal as the mask (M-SLPCEO) are demonstrated. The proposed process can simplify one mask to fabricate GaAs MOSFET and grow reliable gate oxide films as well as side-wall passivation layers at the same time. The 1 μm gate-length MOSFET with a gate oxide thickness of 35 nm shows a transconductance of 90 mS/mm and a maximum drain current density larger than 350 mA/mm. In addition, a short-circuit current gain cutoff frequency f_T of 6.5 GHz and a maximum oscillation frequency f _max of 18.3 GHz have been achieved from the 1 μm×100 μm GaAs MOSFET