Modeling of tunneling P/E for nanocrystal memories

This paper presents a detailed study of the program/erase (P/E) dynamics under uniform tunneling for nanocrystal (NC) memories. Calculating the potential profile and the tunneling currents across the dielectric barriers, we evaluate NC charging and discharging transients during P/E operations. The calculated P/E windows and times compare well with experimental data for memory cells with different oxide thicknesses. The model accounts for the typical features of threshold voltage (V/sub T/) shift as a function of applied gate voltage, and can be used as a valuable tool for optimizing the cell geometry and parameters for maximum performance.     

An endurance evaluation method for flash EEPROM

Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V/sub T/ rollup and cycling V/sub T/ window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V/sub T/ rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted /spl Delta/V/sub T/ degradation slope during constant FN stress can be applied quantitatively to predict the V/sub T/ window closure during Flash cell cycling.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.     

Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact

This letter reports the first full process integration of nanocrystal memory cell with 4.6 F/sup 2/ area ( NOR type), which is achieved by direct tungsten (W) bitline on self-aligned landing plug polysilicon contact. Prior to the nanocrystals (NCs) formation, surface hydroxylation of the tunnel SiO/sub 2/ by exposure to 1:99 hydrogen flouride (HF) is performed to maintain controllability of NCs. Also, the degradation of the tunnel SiO/sub 2/ caused by HF dipping is overcome to some extent through its fluorination. Robust four-threshold voltage (V/sub th/) states for 2-bit operation per cell are observed due to the localized injected charge and V/sub th/ asymmetry from different reading sensitivity to localized charges.     

Space-filling approach for fast window query on compressed images

Based on the space-filling approach, this paper presents a fast algorithm for window query on compressed images. Given a query window of size n/sub 1//spl times/n/sub 2/, the proposed algorithm takes O(n/sub 1/logT+P) time to perform the window query, where n/sub 1/=max(n/sub 1/, n/sub 2/) and T/spl times/T is the image size; P is the number of outputted codes. The proposed algorithm improves the naive algorithm, which needs O(n/sub 1/n/sub 2/log T+P) time, significantly. Some experimentations are carried out to demonstrate the computational advantage of the proposed algorithm. From the experimental results, it is observed that the proposed algorithm has about 72-98% time improvement when compared to the naive algorithm.     

Novel program versus disturb window characterization for split-gate flash cell

In this letter, a new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in V/sub wl/ (word-line)-V/sub ss/ (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program bias variations. This methodology was successfully implemented in 0.18-/spl mu/m triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

Investigation of maximum current sensing window for two-side operation, four-bit/cell MLC nitride-trapping nonvolatile flash memories

Localized charges in a nitride-trapping device provide two-bit/cell operations. Adding multilevel-cells (MLCs) to the physical bits produces a four-bit/cell device. However, it is difficult to get sufficient sensing windows for MLC operation because the left bit and right bit interfere with each other. This letter analyzes the effect of the second bit effect and investigates parameters affecting the sensing current window for physical four-bit/cell operations. The sensing window is found to increase with a higher reading bias, and also with a higher programmed V/sub t/. However, severe second bit effects set in at high V/sub t/, and decreased the sensing window again. An optimal sensing window is found at moderately high V/sub t/.     

Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory

High-quality silicon-nitride (Si/sub 3/N/sub 4/) formed by rapid thermal nitridation is investigated as the tunnel dielectric in a SONOS-type memory device for the first time. Compared to a conventional thermal SiO/sub 2/ tunnel dielectric, thermal Si/sub 3/N/sub 4/ provides 100/spl times/ better retention after 1e5 P/E cycles and better endurance characteristics with low programming voltages. Hence, the SONNS structure is promising for nonvolatile memory applications.     

AlGaInP light-emitting diode with tensile strain barrier reducing layer

A novel tensile strain barrier reducing (TSBR) structure is grown between the window and cladding layers of multi-quantum-well (MQW)-AlGaInP light-emitting diodes (LEDs). The TSBR film (100/spl sim/200 /spl Aring/ of Ga/sub 0.65/In/sub 0.35/P) is of lattice size and valence band energy intermediate between those of window and cladding layers, thus reducing band offset and decreasing device forward bias from 2.55 V to 1.92 V at 20 mA, with concomitant improvements in dynamic resistance and junction heating. The TSBR layer increases power efficiency by 30% at 20 mA and up to 65% at high current conditions. The reduced junction heating of the with-TSBR design may be of significant advantage to device quality, reliability and lifetime, especially for high current applications.     

Stress-related hydrogen degradation of 0.1-/spl mu/m InP HEMTs and GaAs PHEMTs

Hydrogen degradation of III-V field-effect transistors (FETs) is a serious reliability concern. Previous work has shown that threshold-voltage shifts induced by H/sub 2/ exposure in 1-/spl mu/m-channel InP high-electron mobility transitors (HEMTs) can be attributed to compressive stress in the gate due to the formation of TiH/sub x/ in Ti/Pt/Au gates. The compressive stress affects the device characteristics through the piezoelectric effect. This paper examined the H/sub 2/ sensitivity of 0.1-/spl mu/m strained-channel InP HEMTs and GaAs pseudomorphic HEMTs. After exposure to H/sub 2/, the threshold voltage V/sub T/ of both types of devices shifted positive. This positive shift in V/sub T/ is predicted by a model for hydrogen-induced piezoelectric effect. In situ V/sub T/ measurements reveal distinct time dependences of the V/sub T/ shifts, which are also consistent with stress-related phenomena.     

Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials

A detailed investigation of the time evolution for the low-field resistance R/sub off/ and the threshold voltage V/sub th/ in chalcogenide-based phase-change memory devices is presented. It is observed that both R/sub off/ and V/sub th/ increase and become stable with time and temperature, thus improving the cell readout window. Relying on a microscopic model, the drift of R/sub off/ and V/sub th/ is linked to the dynamic of the intrinsic traps typical of amorphous chalcogenides, thus providing for the first time a unified framework for the comprehension of chalcogenide materials transient behavior.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Markov model for threshold-voltage shift in amorphous silicon TFTs for variable gate bias

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in active matrix displays and sensors, in which their operation is typically analog in nature. However, the TFT experiences a V/sub T/ shift with time under gate bias, and the need for a model of the V/sub T/ shift with variable gate bias is imperative for robust circuit design. A model for the V/sub T/ shift under constant and variable gate bias has been presented and agrees with measurement results. The developed model can be easily represented by circuit elements and incorporated into a circuit simulator. As a proof of concept, we use the model to predict the transients of a weighted voltage subtractor circuit.     

Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition Layers

By including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition (IFT) layers, an excellent agreement in terms of both C-V and J-V characteristics is obtained between the experiment and theory for both polarities of gate voltage (V/sub G/) for the first time. The highly precise physical models for gate depletion and gate accumulation bring an oxide thickness extracted from the C-V fitting in a negative V/sub G/ close to that extracted in a positive V/sub G/. It is shown that the physical oxide thickness should be regarded as a distance between the middle points inside the IFT layers in both sides of the gate oxide. In addition, it is found that the tunnel mass is independent of the gate-oxide thickness from 14 to 28 /spl Aring/. It is also shown that the oxide-thickness dependence of the tunnel mass , is ascribable to the C-V-J-V fitting only in the case of a negative polarity of V/sub G/ while neglecting the poly-Si/SiO/sub 2/ IFT layer.     

Experimental investigation of the temperature dependence of InAs-AlSb-GaSb Resonant Interband tunnel diodes

The temperature dependence of the current-voltage (I-V) characteristics of InAs-AlSb-GaSb resonant interband tunnel diodes (RITDs) has been investigated from 223 to 423 K. Several device structures were examined, with tunnel barrier thicknesses from 0.6 to 2.0 nm. For all barrier thicknesses, the peak current density (J/sub p/) decreases slightly as the temperature is increased, while the valley current density (J/sub v/) increases with temperature. We found that the temperature rate of change for the peak current density with temperature (/spl part/J/sub p///spl part/T) is nearly independent of barrier thickness, while J/sub v/ increases more rapidly for devices with thicker barriers. In addition, the peak voltage (V/sub p/) was found to be independent of temperature, regardless of barrier thickness. However, the valley voltage (V/sub v/) was observed to decrease with increasing temperature, with more rapid changes observed for RITDs with thicker barriers. Comparison of the temperature performance of RITDs with different barrier thicknesses shows that devices with thinner barriers have I-V characteristics that are less sensitive to temperature, as well as having larger peak and valley current density and voltage for the temperature range from 223 to 423 K. To our knowledge, this is the first report of the temperature dependence of the device characteristics of Sb-based RITDs as a function of barrier width.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

On the joint source-channel coding error exponent for discrete memoryless systems

We investigate the computation of Csisza/spl acute/r's bounds for the joint source-channel coding (JSCC) error exponent E/sub J/ of a communication system consisting of a discrete memoryless source and a discrete memoryless channel. We provide equivalent expressions for these bounds and derive explicit formulas for the rates where the bounds are attained. These equivalent representations can be readily computed for arbitrary source-channel pairs via Arimoto's algorithm. When the channel's distribution satisfies a symmetry property, the bounds admit closed-form parametric expressions. We then use our results to provide a systematic comparison between the JSCC error exponent E/sub J/ and the tandem coding error exponent E/sub T/, which applies if the source and channel are separately coded. It is shown that E/sub T//spl les/E/sub J//spl les/2E/sub T/. We establish conditions for which E/sub J/>E/sub T/ and for which E/sub J/=2E/sub T/. Numerical examples indicate that E/sub J/ is close to 2E/sub T/ for many source-channel pairs. This gain translates into a power saving larger than 2 dB for a binary source transmitted over additive white Gaussian noise (AWGN) channels and Rayleigh-fading channels with finite output quantization. Finally, we study the computation of the lossy JSCC error exponent under the Hamming distortion measure.     

Forward body bias for microprocessors in 130-nm technology generation and beyond

Device and test chip measurements show that forward body bias (FBB) can be used effectively to improve performance and reduce complexity of a 130-nm dual-V/sub T/ technology, reduce leakage power during burn-in and standby, improve circuit delay and robustness, and reduce active power. FBB allows performance advantages of low-temperature operation to be realized fully without requiring transistor redesign, and also improves V/sub T/ variations, mismatch, and saturation transconductance and output resistance product (g/sub m//spl times/r/sub o/).