数字电路并发差错定位的概念与基本结构

在数字电路的并发差错检测理论的基础上,建立了一种并发差错定位数字电路理论,它包括并发差错定位电路有关特性的定义,实现基本功能的电路的模块结构及其内部模块之间互连的条件,数字电路的并发差错定位指的是电路在政党工作条件下,无需任何外加用于定位电路故障的输入矢量就能自动定位其内部的故障,一个基本并发差错定位电路由实现电路基本功能的基本功能模块和实现电路差错定位功能的定位器级联所构成,系统地定义了表征并发     

一种离散余弦变换电路的并发故障检测结构…

本文提出了一种离散余弦变换 (DCT)电路的并发故障检测结构。DCT采用 B.G.L ee算法蝶型结构实现 ,检测采用的方法是基于算法的并发故障检测容错方法。与其它并发故障检测容错结构相比 ,本文提出的并发故障检测 DCT结构在硬件及时间冗余度上均优越     

航空发动机容错控制系统设计

航空发动机是一个结构复杂、非线性强的多变量控制对象.控制系统的高可靠性是最重要的技术指标之一.而容错控制为提高系统的可靠性、可维护性和有效性开辟了一条新途径.文中介绍了基于航空发动机容错控制的基本原理和方法,研究了控制系统在反馈信号故障情况下的容错控制问题,该系统可以对失效的检测数据做出实时估计并反馈信号,从而达到对故障容错的目的.     

基于COTS技术的高可靠通用容错计算机容错机制研究

本文提出并实现了一种基于COTS部件、容错机制智能实现的、新颖的通用高可靠容错计算机系统。基于容错功能与用户应用相分离的原则，应用自主设计的智能管理模块。实现对COTS部件内部状态的可观察性。详细分析了系统的容错机制。利用提出的故障逃逸模型，分析了系统中的层次化故障检测和保护措施并估计了系统故障覆盖率。     

双机热备容错逻辑控制电路设计与仿真

针对传统数字电路系统冗余设计复杂、切换时间长、实现电路体积大等问题,提出一种双机热备容错逻辑控制电路的设计方案.使用VHDL语言设计、一片CPLD芯片实现工作微处理器系统的故障检测与主、备微处理器系统的实时切换等时序控制功能.时序仿真结果表明,该电路判断故障成功率高,切换时间短,可以满足强实时性嵌入式系统的双机热备冗余设计.在高可靠性的微机保护系统等应用场合,该硬件冗余设计方案具有工程设计指导意义.     

网口容错在嵌入式设备中的设计与实现

针对嵌入式网络设备的服务可靠性问题,现有的网口容错主要采用双网卡冗余设计,研究针对单网卡多网口的情况,提出了一种网口容错方法,该方法能有效利用系统带宽资源。提出的网口容错方法包括一种网口状态检测机制和故障网口服务数据迁移方法,并设计了相应的功能模块。故障检测模块实现基于Loopback的检测方法,容错处理模块则实现在检测到故障后,可将故障网口的服务负载数据根据迁移策略迁移到其余正常网口。所提出的方法实现了对网口工作状态的快速检测和负载数据的有效容错。该方法具有应用无关性、资源占用率低的特点,通过测试验证了该方法的可行性。     

基于神经网络的非线性系统故障检测及容错控制方法

利用神经网络的非线性建模能力，提出了一种非线性系统的故障检测及容错控制方法。在本方法中，首先应用神经网络设计故障估计器，在线估计系统故障向量，实现故障检测；在此基础上，引入补偿控制器，消除故障对系统运行的影响，从而实现容错控制。同时基于Ｌｙａｐｕｎｏｖ方法进行了稳定性分析。     

端口故障粒度划分的虚通道动态分配式容错路由器设计

高可靠性是高性能片上网络路由器发展的重要方面,针对目前虚通道动态分配式路由器端口易发生故障的问题,提出了一种基于端口故障粒度划分的容错路由器设计。首先,结合虚通道动态分配方式的特殊性以及故障发生特性,建立了一种粒度划分的端口故障与拥塞预测模型;然后在此模型的基础上结合实时故障检测方法设计相关容错电路,增加邻端口共享模块,设计容错读写指针控制逻辑电路;最后依据设计的电路提出容错与拥塞缓解方案。实验结果表明,在各种端口故障模式下,该路由器均能保持较好的容错特性,性能衰减较小,并且具有较好的性能提升与面积开销比。     

多变量反馈控制系统的完整性分析

以线性时不变多输入多输出反馈控制系统为研究对象，建立了基于ｋ个传感器和ｎ个执行器失效的故障系统数学模型，并提出了仍能保证系统稳定性的控制器必须满足的条件，从而为设计具有容错能力的控制系统提供了理论依据。     

基于动态事件触发的混沌系统故障容错同步问题

针对混沌系统故障容错同步问题进行研究,设计基于动态事件触发的同步控制器以实现混沌系统的故障容错同步.首先,针对系统中存在的故障环节构造故障容错的系统模型,在此基础上采用输入-状态稳定性(ISS)的方法,将控制器求解问题转化为求解所对应故障容错系统的稳定性问题;然后,通过构造Lyapunov函数给出混沌系统故障容错同步的充分条件,通过引入动态变量,使得所设计的触发条件可以根据系统的运行状态进行动态调整,在实现系统故障容错同步的同时,最大程度地降低网络的占用率;最后,通过数值仿真验证所提出方法的有效性.     

交替互补定位器及其用于双模比较冗余结构的差错定位

双模比较冗余结构是一种广泛应用的低成本容错结构。当两个冗余模块之一发生故障时,比较器将给出差错检测指示输出,该输出既可以按中断信号形式通知系统作出相应的差错处理,也可以按硬件信号形式直接用于终止系统工作或启动重构,目的是防止故障冗余结构给出错误输出,或者确保系统能够提供连续的服务。这种冗余结构的缺点是比较器不能确切指明故障模块,并因此而需要较大的时间开销来完成系统重构和恢复操作。为解决这一问题,提出了一种具有并发输出差错定位功能的双重比较冗余结构。其中单个冗余模块的输出是一个交替矢量,两个冗余模块的输出形成了一个交替互补矢量,该矢量送入一个交替互补定位器。在正常输入情况下,根据定位器的输出就可以确定冗余系统是无差错的、还是冗余模块或定位顺本身存在故障。交替互补定位器由D型触发器和通用门电路构成,它被证明为是一个完全故障定位的定位器。由于所提出的双模比较冗余结构是基于时间冗余原理工作的,因此它适用于对速度要求并不是非常苛刻的容错系统。     

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (P_detection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average P_detection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.     

高性能处理器的差错校正技术

随着芯片密度的不断增加和对可靠性要求的不断提高,高性能处理器的容错设计越来越受到关注.对近年来高性能处理器的差错校正技术进行了分析和比较,它们被分为时钟级差错恢复、指令级差错恢复、线程级差错恢复以及重构等4类,研究对象包括研究方案、原型和产品.研究结果表明,以片上多处理器和/或同时多线程为特征的高性能处理器除了沿用传统的容错技术之外,多以固有的、旨在为改善性能而重复设置的硬件资源为基础来设计容错机制和调度方案.     

Fault-tolerant computing: fundamental concepts

The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detection, masking, and correction; error detection and correction codes; self-checking logic; module replication for error detection and masking; protocol and timing checks; fault containment; reconfiguration and repair; and system recovery     

Observer‐based fault diagnosis and self‐restore control for systems with measurement delays

The problems of fault diagnosis and fault‐tolerant control are considered for systems with measurement delays. In contrast to the present fault diagnosis and fault‐tolerant control approaches, which consider only the input delay and/or state delay, the main contribution of this paper consists of proposing a new observer‐based reduced‐order fault diagnoser construction approach and a design approach to dynamic self‐restore fault‐tolerant control law for systems with measurement delays. First, the time‐delay system is transformed into a delay‐free system in form by a special functional‐based delay‐free transformation approach for measurement delays. Then, the fault diagnosis is realized online via the proposed reduced‐order fault diagnoser. Using the results of fault diagnosis, two dynamic self‐restore control laws are designed to make the system isolated from faults. A numerical example demonstrates the feasibility and validity of the proposed scheme. © 2012 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society     

Fault-tolerant systems with concurrent error-locating capability

Fault-tolerant systems have found wide applications in military,industrial and commercial areas.Most of these systems are constructed by multiple-modular redundancy or error control coding techniques,They need some fault-tolerant specific components (such as voter,switcher,encoder,or decoder) to implement error-detecting or error-correcting functions.However, the problem of error detection location or correction for fault-tolerance specific components them-selves has not been solved properly so far.Thus ,the dependability of a whole fault-tolerant system will be greatly affected.This paper presents a theory of robust fault-masking digital circuits for characterizing fault-tolerant systems with the ability of concurrent error location and a new scheme of dual-modular redundant systems with partially robust fault-masking prperty.A Basic robust fault-masking circuit is composed of a basic functional circuit and an error-locting corrector,Such a circuit not only has the ability of concurrent error correction,but also has the ability of concurrent error location.According to this circuit model ,for a partially robust fault-making dual-modular redundant system,two redundant modules based on alternating-complementary logic consist of the basic functional circuit.An error-correction specific circuit named as alternating-complementary corrector is used as the error-locating corrector.The performance(such as hardware complexity, time delay) of the scheme is analyzed.     

Almost certain fault diagnosis through algorithm-based faulttolerance

Algorithm-based fault tolerance has been proposed as a technique to detect incorrect computations in multiprocessor systems. In algorithm-based fault tolerance, processors produce data elements that are checked by concurrent error detection mechanisms. We investigate the efficacy of this approach for diagnosis of processor faults. Because checks are performed on data elements, the problem of location of data errors must first be solved. We propose a probabilistic model for the faults and errors in a multiprocessor system and use it to evaluate the probabilities of correct error location and fault diagnosis. We investigate the number of checks that are necessary to guarantee error location with high probability. We also give specific check assignments that accomplish this goal. We then consider the problem of fault diagnosis when the locations of erroneous data elements are known. Previous work on fault diagnosis required that the data sets produced by different processors be disjoint. We show, for the first time, that fault diagnosis is possible with high probability, even in systems where processors combine to produce individual data elements     

Concurrent online testing of identical circuits using nonidentical input vectors

Current designs may contain several identical copies of the same circuit (or functional unit). Such circuits can be tested by comparing the output vectors they produce under identical input vectors. This alleviates the need to observe the output response, and facilitates online testing. We show that testing of identical circuits by output comparison can be done effectively even when the input vectors applied to the circuits are not identical. This allows concurrent online testing even when the circuits are not driven from the same source during functional operation. We investigate several issues related to this observation. We investigate the use of both structural and functional analysis to identify situations where nonidentical input vectors can be used for fault detection based on output comparison. We also consider the use of observation points to improve the fault coverage. We present experimental results to support the discussion and the use of nonidentical input vectors for concurrent online testing of identical circuits.     

New structures of the concurrent error detection systems for logic circuits

Proposed were new structures for concurrent error detection systems of the combinatorial logic circuits based on the codes with summation of the weighted transitions and their modifications. They were compared with the traditional systems of duplication and check by the Berger code. The structure based on the code with summation of the weighted transitions allowed one to improve the index of realization complexity as compared with the duplication system by 4 % on the average. The structure obtained by modifying the code with summation of the weighted transitions into the optimal code enables one to improve this index almost twice as much as compared with the system of checking by the Berger code. At that, this system has a better index of error detection. In certain cases, the structure of the concurrent error detection system on the basis of the optimal code is superior in complexity to the system of parity check.