BIST scheme for DAC testing

A low-cost, built-in self-test (BIST) scheme for a digital-to-analogue converter (DAC) is presented. The basic idea is to convert the DAC output voltages corresponding to different input codes into different oscillation frequencies through a voltage controlled oscillator (VCO), and further transfer these frequencies to different digital codes using a counter. According to the input and output codes, performances of a DAC, such as offset error, gain error, differential nonlinearity (DNL), integral nonlinearity (INL), could be effectively detected by simply using digital circuits rather than complex analogue ones. In addition, the annoying DAC output noise could be naturally filtered out by this BIST method     

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.     

An I/Q channel 12-bit 120?MS/s CMOS DAC with deglitch circuits

This paper describes an I/Q channel 12bit 120?MS/s DAC with deglitch circuits. The proposed DAC implemented in a 0.35???m CMOS n-well process employs three stage 4 bit thermometer decoders and deglitch circuits to minimize glitch energy and linearity error. The measurement results show a ±1.5?LSB/±1.3?LSB of INL/DNL and 31 pV·s of glitch energy. ENOB and SFDR are measured to be 10.5 bit and 71.09?dB at sampling frequency of 120?MHz and input frequency of 1?MHz with a total power consumption of 105?mW. Linearity error between I-channel DAC and Q-channel DAC is measured to be approximately 1.5?mV, i.e. the accuracy of 13 bit.     

BIST structure for DAC testing

A built-in self-test (BIST) structure for digital-to-analogue converter (DAC) testing is presented. The basic idea is to divide the input codes (0, 1, ..., 2ⁿ-1) of the DAC under test into a number of segments. The DAC output voltages corresponding to different codes in the same segment are amplified to the same voltage value. Such that one single reference voltage can be used to test all codes in the same segment. By this method, the number of reference voltages required for DAC testing can be greatly reduced. We show that offset error, gain error, integral nonlinearity (INL) and differential nonlinearity (DNL) are effectively detected in the proposed BIST structure     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

一种GSM无线发射系统中的低功耗数模转换器

针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源...     

一种带有插值滤波器的8位650MHz采样速率数字模拟转换器

针对OFDM-UWB标准超宽带收发系统中数模转换器(DAC)的要求,设计了一款8位650MHz采样速率电流驱动型数模转换器(Current-steering DAC)。为了提高静态性能,本设计通过蒙特卡洛分析确定电流源最佳尺寸并采用双中心版图技术;为了提高动态性能,文中采用共源共栅电流源结构,对开关电压降摆幅处理并在数字输入端前加入插值滤波器。测试结果表明,DAC的积分非线性(INL)和差分非线性(DNL)分别为0.3LSB和0.41LSB,650MHz转换速率下带内奈奎斯特无杂散动态范围(SFDR)为41dB。整体面积为1.8cm×1.3cm,其中DAC面积为0.8cm×0.8cm。     

High-level modeling of resistor string based digital-to-analog converters

To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented in MATLAB^TM environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects. The model was successfully used to design a 10bit resistor string DAC in a 0.18 μm BCD technology with DNL and INL lower than 1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art.     

A 14-b 32 MS/s pipelined ADC with fast convergence comprehensive background calibration

This paper presents the first aggressively calibrated 14-b 32 MS/s pipelined ADC. The design uses a comprehensive digital background calibration engine that compensates for linear and nonlinear errors as well as capacitor mismatch in multi-bit DAC. Background calibration techniques that estimate the errors by correlating the output of ADC with the calibration signal have a very slow convergence rate. This paper also presents a fully digital technique to speed up the convergence in the error estimation procedure. By digitally filtering the input signal during the error estimation, the convergence rate of the calibration has been improved significantly. Implemented in TSMC 0.25 μm technology, the pipelined ADC consumes 75 mA from 2.5 V and occupies 2.8 mm² of active area. Measurement results show that calibration significantly improved dynamic (SNDR, SFDR) as well as static (DNL, INL) performance of the ADC.     

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.     

12bit高稳定性数模转换器设计

设计了一款12 bit高稳定性控制类数模转换器(DAC),该DAC集成了带有稳定启动电路的新型低失调带隙基准源(BGR),改善了基准电路的稳定性以及对温度和工艺的敏感性;DAC采用了改进的两级电阻串结构,通过开关电阻匹配和特殊版图布局,在既不增加电路功耗又不扩大版图面积的前提下,提高了DAC的精度并降低了工艺浓度梯度对整体性能的影响.基于CSMC 0.5 μm 5 V 1P4M工艺对所设计的DAC芯片进行了流片验证.测试结果表明:常温下DAC的微分非线性(DNL)小于0.45 LSB,积分非线性(INL)小于1.5 LSB,并且在-55～125℃内DNL小于1 LSB,INL小于2.5 LSB;5V电源电压供电时功耗仅为3.5 mW,实现了高精度、高稳定性的设计目标.     

应用于视频中的R2R梯形电阻网络DAC

本文设计了一款用于视频中的R2R梯形电阻网络数模转换器。其电路结构包含8位R2R梯形电阻网络DAC、输出放大器、低电平转高电平电路、模拟开关、参考电压和锁存器电路。电路设计是基于CSM0.11μm CMOS Logic工艺,经HSPICE仿真表明,DAC的积分非线性误差（INL）和微分非线性误差（DNL）分别小于1.65LSB和0.23LSB,功耗仅为3.86mW。     

基于QN旋转布局的10位500 MS/s分段电流舵DAC

针对分段电流舵数/模转换器（Digital-to-Analog Converter，DAC），通过理论分析和推导，研究电流源阵列系统失配误差和寄生效应对非线性的影响，采用电流源阵列Q^N旋转游走版图布局方案，能够减小电流源系统失配的一次误差，而且版图布线简单，由寄生效应引起的电流源失配较小，利于DAC非线性的优化.基于0.18μm CMOS，采用"6+4"的分段结构，设计了一种10位500MS/s分段电流舵DAC，流片测试结果表明，在输入频率为1.465MHz，采样速率为500MS/s的条件下，无杂散动态范围（Spurious Free Dynamic Range，SFDR）为64.9dB，有效位数（Effective Number of Bits，ENOB）为8.8 bit，微分非线性误差（Differential Non-linearity，DNL）和积分非线性误差（Integral Non-linearity，INL）分别为0.77LSB和1.12LSB.     

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.     

一种用于电流舵DAC的开关顺序优化技术

提出了一种用于电流舵DAC的开关顺序优化技术。首先,将高位电流源阵列拆分成四个部分并位于四个象限中,在每个象限中采用开关顺序优化技术消除电流源阵列由PVT变化而带来的二阶梯度幅值误差;其次,对开关顺序优化后的电流源阵列根据幅值变化进行排序并重组,形成最终的电流源及开关顺序,消除了一阶梯度幅值误差和其他残余误差。与常规开关顺序优化技术相比,该技术能更有效地降低幅值误差,提高了DAC的静态性能。为了验证提出的开关顺序优化技术,基于40 nm CMOS工艺制作了一个12位200 MS/s采样频率的电流舵DAC。测试结果表明,实施开关顺序优化技术的DAC的INL、DNL分别从0.63 LSB、0.37 LSB降低到0.54 LSB、0.25 LSB。     

Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator

This paper describes algorithms for generating a low-distortion single-tone signal, for testing ADCs, using an arbitrary waveform generator (AWG). The AWG consists of DSP (or waveform memory) and DAC, and the nonlinearity of the DAC generates distortion components. We propose here to use DSP algorithms to precompensate for the distortion. The DSP part of the AWG can interleave multiple signals with the same frequency but different phases at the input to the DAC, in order to precompensate for distortion caused by DAC nonlinearity. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of this approach.     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

一种10位电容电阻混合型双极性D/A转换器

在加速度计中,需要数模转换器(DAC)提供一个稳定的偏压来消除重力加速度,要求DAC具有高精度、单调性和小面积等特性。为了解决传统电阻型DAC存在的大面积和传统电容DAC中存在的非单调性等问题,提出了一种电容电阻混合型DAC结构,并设计了一个10位的DAC,用于提供稳定偏压。提出一种新的电容共质心的版图布局,提高了DAC的精度。该DAC在0.5μm CMOS工艺上得以验证实现,微分非线性误差(DNL)最大为0.50LSB,积分非线性误差(INL)最大为0.82LSB,在5V和-5V的双电源供电条件下,芯片功耗为16mW,完全满足了工程需求。     

A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-/spl mu/m CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution.     

Multibit Delta-Sigma Modulator With Noise-Shaping Dynamic Element Matching

This paper describes a fifth-order multibit low-pass delta-sigma modulator employing a proposed noise-shaping dynamic element matching (NS-DEM) technique to remove DAC nonlinearity error. Unlike most existing DEMs that trade SNR for SFDR, the proposed technique improves both SFDR and SNR. The noise shaping is incorporated in the first integrator of the loop filter without any additional analog circuitry. The fabricated modulator chip achieves 94-dB SFDR and 78-dB DR in 2.2-MHz BW and meets the ${rm ADSL2}+$ specifications.