The development of biaxial alignment in yttria-stabilized zirconia films fabricated by ion beam assisted deposition

Yttria-stabilized zirconia (YSZ) films were deposited using ion assisted, electron beam deposition (IBAD) on Pyrex, quartz, Hastelloy, and polycrystalline zirconia substrates. Film orientation was studied as a function of IBAD fabrication conditions. Film texture from several populations of biaxially aligned grains has been observed. The ion beam is shown to induce biaxial alignment of all grain orientations. Specifically, grains with (200), (311), and (111) normal to the substrate surface are biaxially aligned. The ion beam induces biaxial alignment at all angles of incidence, not just those corresponding to YSZ channeling directions. The development of (200) biaxial alignment on Pyrex is examined as a function of thickness. Biaxially aligned IBAD YSZ films were deposited on amorphous and polycrystalline substrates without active heating. Biaxial alignment development with IBAD is shown to be consistent with a previously proposed growth and extinction model.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

聚焦离子束组合装置及应用

聚焦离子束技术是一种集形貌观测、定位制样、成分分析、薄膜淀积和无掩膜刻蚀各过程于一身的新型微纳加工技术。对电子离子双束纳米工作站,聚焦离子束、扫描电镜和Ar离子束构成的“三束”显微镜系统的原理和应用作了详细介绍,同时也对聚焦离子束-分子束外延组合装置、聚焦离子束与二次离子质谱仪(SIMS)的组合装置以及单轴聚焦离子/电子束(FIEB)装置作了简单介绍。     

Deposition Characteristics of AlN Thin Film Prepared by the Dual Ion Beam Sputtering System

In this experiment, a radio frequency dual ion beam sputtering (DIBS) system was used to prepare aluminum nitride (AlN) films with a bottom Al electrode on a Si (100) substrate. After systematic testing of the processing variables, a high-quality film with preferred c-axis orientation was grown successfully on the Si (100) substrate with an Al target under 700 eV energy flux, N₂/(N₂ + Ar) ratio of 55%, and 4 × 10⁻⁴ torr in vacuum. The characteristics of the deposited AlN thin films were studied by x-ray diffraction (XRD), scanning electron microscope (SEM), transmission electron microscope (TEM), secondary ion mass spectrometry (SIMS), and electronic spectroscopy for chemical analysis (ESCA). The surface roughness was also measured. It was found that AlN films prepared by DIBS at room temperature are better than those prepared at 300°C, and those prepared with an Al target are better than those prepared with an AlN target. The inferiority of AlN films prepared with AlN targets is due to the AlN bond being broken down by the ion beam source.     

Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

Dry etching of GaN using chemically assisted Ion beam etching with HCI and H2/Cl2

The dry etching characteristics of GaN were investigated using chemically assisted ion beam etching (CAIBE) with HCI and H₂/Cl₂ gas. Etch rates using CAIBE/HC1 were investigated as a function of Ar ion beam energy and substrate temperature. These results were compared to CAIBE/C1₂. Etch rates were also investigated for CAIBE/H₂/Cl₂ for various ratios of H₂:C1₂. Highly anisotropic submicron lines are demonstrated using CAIBE/HC1. Auger electron spectroscopy was used to investigate surface stoichiometric changes of samples etched with CAIBE/HC1, CAIBE/H₂/Cl₂,, and CAIBE/C1₂. The diffusion of deuterium into GaN during etching was also investigated using secondary ion mass spectrometry.     

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperature-dependent Cu and multilayered graphene nanoribbon (MLGNR)-based nano-interconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

Strain relaxation in silicon ion molecular beam epitaxy on silicon (001) substrates during aging

Silicon strained epitaxial films were grown on Si (001) substrates by low energy ion beam assisted molecular beam epitaxy. Films grown in the range of 450– 550°C with concurrent Ar⁺ ion bombardment (100 eV) were characterized using x-ray diffraction and transmission electron microscopy and found to be disloca-tion free and ununiformly strained. During aging, the strained layers stay stable until 500°C. Relaxation of most of the strain occurred at temperatures of 500-650°C. At higher aging temperatures, the strained layers relaxed by the formation of dense dislocation structures.     

Chemically assisted ion beam etching of gallium nitride

Chemically assisted ion beam etching of gallium nitride (GaN) grown by metalorganic chemical vapor deposition has been characterized using an Ar ion beam and Cl₂gas. The etch rate of GaN was found to increase linearly with Ar ion beam current density, increase linearly then saturate with Ar ion beam energy, vary slightly with Cl₂ flow rate, and lastly, increase moderately with substrate temperature. Etch rates as high as 330 nm/min were obtained at high beam energies and 210 nm/min at a more nominal level of 500 eV. The anisotropy of etched profiles improved in the presence of Cl₂ in comparison to those etched by Ar ion milling only. Elevated substrate temperatures further enhanced the anisotropy to obtain near-vertical profiles for fairly deep-etched structures. Auger electron spectroscopy was used to investigate etch-induced surface changes. Oxygen contamination was observed on the as-etched surface but a dilute HC1 treatment restored the stoichiometry of the material to its unetched state.     

Synthesis of low resistivity complex oxides on MgO using Pt as buffer layer

Highly crystalline SrRuO₃ (SRO) and La_0.5Sr_0.5CoO₃ (LSCO) thin films were deposited on (100) Pt/ MgO by pulsed laser deposition. The films were mainly (001) textured normal to the substrate surface with a high degree of in-plane orientation with respect to the substrate’s major axes. These films were characterized using x-ray diffraction, Rutherford backscattering, four-point probe resistivity measurement, and transmission electron microscopy. The room temperature resistivity for LSCO and SRO films on Pt/MgO was found to be ∼35 and ∼40 μΩ-cm, respectively. An ion beam minimum channeling yield of ∼43% and ∼33% was obtained for LSCO and SRO films, respectively. The interface between Pt and oxide was found to be smooth and free from any interfacial diffusion. This result showed that high-quality low resistivity oxide thin films can be deposited on Pt.     

Electron beam induced current investigations of active electrical defects in silicon due to reactive ion etching and reactive ion beam etching processes

Reactive ion etching and reactive ion beam etching are common tools for anisotropic etch processes in silicon microdevice fabrication; but, unfortunately, they also create radiation damage in the etched surface. We have studied the electrically active defects by measuring the recombination of carriers with the help of the electron beam induced current (EBIC) mode of a secondary electron microscope. We have measured the temperature behavior of the samples by annealing studies and the temperature dependent EBIC signal for several p-doped silicon wafers and obtained different shaped curves. Theoretical EBIC models developed with the assumption of a reduced net carrier concentration in the etched areas agree with our experimental results.     

Metal lift-off using a trilevel resist system for electron beam lithography

Multilayer resist optical lithography is transposed into trilevel resist electron beam lithography. A thin electron-sensitive multilayer resist is exposed in a dedicated scanning transmission electron microscope. The upper resist layer is chemically developed, the underlying layers are patterned by reactive ion etching. Very fine titanium lines (1 μm to 30 nm) are obtained after evaporation and lift-off process.     

Study of high-quality epitaxial YBCO thin films grown directly on Y-Cut LiNbO3

Pulsed laser deposition was used to deposit high-quality YBa₂Cu₃O_7-δ (YBCO) thin films directly on y-cut LiNbO₃ substrates. The as-deposited YBCO films had a high degree of in-plane orientation and showed superconducting transition temperature (T_co) at 91K with a transition width of less than IK. Transport critical current densities were found to be ∼10⁶ A/cm² at 77K and zero field. An ion beam minimum channeling yield of 16% was obtained for YBCO films, indicating high crystallinity. High-resolution transmission electron microscopy studies showed that the interface between the film and the substrate was quite smooth and free from interfacial interdiffusion. The defects in thin films are also identified. The work showed that high-quality high T_c thin films can be deposited directly on LiNbO₃. Novel devices based on the properties of both YBCO and LiNbO₃ could be realized based on these results.     

Investigation of microstructural processes during ultrasonic wedge/wedge bonding of AlSi1 wires

The wedge microstructure of AlSi1 wire bonds as well as the interface between the bonding wire and the Cu/Ni/Au metallization layer especially for chip on board (COB) assemblies was investigated by focused ion beam (FIB), transmission electron microscopy (TEM), and microhardness measurements. The as-received wires were characterized by fiber texture of 〈111〉 and 〈100〉 orientation. With increasing ultrasonic (US) power, the results indicate recrystallization of the grain structure and decreasing microhardness inside the bonded wedge contacts. The interface between the AlSi1 wire and the Cu/Ni/flash-Au metallization layer of the optimized bonds consists of a closed crystalline Au layer. Above this Au layer, a second zone consisting of intermetallic phases was analyzed and identified by electron diffraction as Au₈Al₃.     

硅基单电子晶体管的可控制备

采用电子束曝光、感应耦合等离子体刻蚀和热氧化等工艺技术,通过独特的图形反转设计,即在电子束曝光时采用负的曝光图形,并以电子束曝光的光刻胶作为掩膜进行干法刻蚀,通过后续的干法热氧化等工艺,在磷离子重掺杂的绝缘体上硅基底上成功地制备出单电子晶体管。该方法具有高精度、结构可控、可重复和加工成本低的优点,可作为一种批量制备单电子晶体管的工艺技术。所制备的单电子晶体管在2.6 K到100 K的温度范围内呈现出明显的库仑阻塞效应,导通电阻小于100 kΩ。该单电子晶体管将成为高速、高灵敏度射频电路的关键器件。     

Ion beam-assisted planarization of chemically vapor deposited diamond thin films using electron cyclotron resonance plasma

The high inherent surface roughness of as-deposited polycrystalline diamond films has made effective planarization processing of these films essential for most industrial applications. We have investigated the efficacy of ion beam sources for planarization in an electron cyclotron resonance plasma system using both direct substrate biasing and an accelerating grid system. Rough polycrystalline diamond films were synthesized using hot filament chemical vapor deposition. Both the etching rates and the resultant surface roughnesses were found to decrease as the angle of incidence (relative to the substrate surface normal) of the ion beam was increased. In the case of direct biasing of the sample, acicular features were observed following processing at higher incident angles. The use of double ion-extraction grids in conjunction with concomitant sample rotation was found to produce more uniform planarization of the diamond films. The rate of surface roughness reduction was found to be nonlinear and decreased with time. For both ion extraction methods investigated, the average film roughness (R_a) was significantly reduced from 0.2 to 0.05–0.06 μm.     

ENIG Corrosion Induced by Second-Phase Precipitation

Materials analysis of a flip-chip package lot with solder bump interconnect failures revealed a new mechanism for corrosion of electroless nickel immersion gold surface finish. Detailed scanning and transmission electron microscopy (SEM and TEM) in conjunction with focused ion beam microscopy and electron dispersion analysis of the unsoldered ball grid array substrate pads on packages that exhibited flip-chip solder bump interconnect failures revealed an unusual and subtle defect in the original Ni(P) layer, which was ultimately responsible for flip-chip joint failure. Detailed TEM analysis of the defect regions showed that they consisted of Ni(P) particles of slightly different composition than the bulk Ni(P) layer. Microstructure changes around these incorporated particles indicated that the second-phase particles were deposited from the plating bath during the Ni(P) growth stage. The second-phase particles provided additional surface area for nucleation and growth of Ni(P). Ultimately, a low-density boundary region in the growing Ni(P) layer formed where the particle-induced growth front and the planar Ni(P) film growth front intersected. This low-density interface eventually terminated at the surface of the Ni(P) layer. In addition the growth from the second-phase particle created localized surface topology that was different than that of the surrounding Ni(P) layer. The low-density interfaces as well as the surface topology led to enhanced corrosion of the Ni(P) layer when exposed to the immersion gold plating process. In some cases the corrosion was severe enough to create voids in the Ni(P) layer. The exposed, oxidized Ni(P) surfaces in and around these enhanced corrosion regions did not wet when exposed to solder. This led to degradation in the strength of the solder joint and subsequent solder interconnect failure.     

Emerging interconnects: a state-of-the-art review and emerging solutions

Aluminium was a primary material for interconnection in integrated circuits (ICs) since their inception. Later, copper was introduced as interconnect material which has better metallic conductivity and resistance to electromigration. As the aggressive technology scaling continues, the copper resistivity increased because of size effects, which causes increase in delay, power dissipation and electromigration. The need to reduce the resistor-capacitor??????? delay, dynamic power utilisation and the crosstalk commotion is as of now the fundamental main impetus behind the presentation of new materials. The purpose of this paper is to do a survey of interconnect material used in IC from introduction of ICs to till date. This paper studies and reviews new materials available for interconnect application which are optical interconnects, carbon nanotube (CNT), graphene nanoribbons (GNRs) and silicon nanowires which are alternatives to copper. While doing a survey of interconnect material, it is found that multiwalled CNTs, multilayer GNR and mixed CNT bundles are promising candidates and are ultimate choice that can strongly address the problems faced by copper but on integration basis copper would last for coming years.