Quantifying memory effects in RF power amplifiers

This paper proposes a system-level behavioral model for RF power amplifiers (PAs), which exhibit memory effects, that is based on the parallel Wiener system. The model extraction is performed using two-tone intermodulation distortion (IMD) measurements with different tone frequency spacings and power levels. It is found that by using such a model, more accurate adjacent-channel power-ratio levels may be predicted for high PAS close to the carrier frequency. This is validated using IS-95B CDMA signals on a low-power (0.5 W) class-AB PA, and on a high-power (45 W) class-B PA. The model also provides a means to quantify memory effects in terms of a figure-of-merit that calculates the relative contribution to the IMD of the memoryless and memory portion of the PA nonlinearity. This figure-of-merit is useful in providing an estimate of the amount of correction that a memoryless predistortion system may have on PAS that exhibit memory effects.     

Neural-network-based adaptive baseband predistortion method for RF power amplifiers

An adaptive baseband predistortion method for RF power amplifier (PA) linearization is proposed and experimentally demonstrated. The predistortion component is implemented by a single-input dual-output multilayer perceptron (MLP). Both amplitude-to-amplitude and amplitude-to-phase distortion products are compensated by backpropagation training of the neural network including the response of the PA. Effects of modulator and demodulator imperfections on system performance are examined. Measurements on a system prototype reveal a significant linearity improvement that reaches 25 dB.     

无线通信中有记忆功率放大器的一种预失真方法

在WCDMA等宽带通信系统中,射频功率放大器记忆效应明显,传统的无记忆预失真技术无法达到理想的线性化效果.分析功放的记忆效应,并提出一种适合于有记忆射频功率放大器的顸失真方法.该方法首先基于记忆多项式构造预失真器,然后采用间接学习结构设计预失真系统,并运用限定记忆递推最小二乘算法更新预失真器参数,以跟踪放大器特性的变化.仿真结果表明,该方法能较好地补偿射频功放的非线性失真和记忆效应.     

A hybrid digital/RF envelope predistortion linearization system for power amplifiers

This paper presents an adaptive wide-band digitally controlled RF envelope predistortion linearization system for power amplifiers (PAs). A field-programmable gate-array-based lookup table is indexed by a digitized envelope power signal, and instantaneously adjusts the input signal amplitude and phase via an RF vector modulator to compensate for the AM-AM and AM-PM distortion. The advantages of this predistortion architecture over conventional baseband digital approaches are that a 20%-33% wider correction bandwidth is achievable at the same clock speeds, and linearization can be performed without the need for a digital baseband input signal. The timing match between the input RF signal and predistorting signal, which is one of the critical factors for performance, was investigated and adjusted to obtain optimum performance. Using three-carrier cdmaOne and wide-band multitone signals, the linearization performances for a 0.5-W GaAs heterostructure field-effect transistor, a 90-W peak-envelope-power (PEP) silicon LDMOS PA, and a 680-W PEP LDMOS PA were examined. In addition, the predistortion performance variation for different signals was studied in terms of signal envelope statistics, output powers, and PA power capacities.     

An adaptive digital predistortion for compensating nonlinear distortions in RF power amplifier with memory effects

In this paper, an adaptive digital predistortion based on a memory polynomial model is proposed in order to linearize the power amplifier with memory effect. The coefficients of the power amplifier model have been extracted using a least square method and those of predistortion have been identified by applying an indirect learning structure. Finally, the performance of digital predistortion has been demonstrated using the simulation of the power amplifier and the digital predistortion excited by a modulated 16 QAM signal in Matlab software. According to the simulation results, the criterion of adjacent channel power ratio (ACPR) declined by around 15 dB and the input/output power spectrum density of the power amplifier has quite similar curves. The linearized power amplifier output spectrum demonstrates the superiority of the proposed predistorter in eliminating the spectral regrowth which is caused by the memory effect in comparison to the other linearization methods.     

基于坐标变换的射频功放预失真参数估计方法

在低中频预失真器构架的基础上,提出了一种基于坐标变换的预失真参数估计方法,从而降低了传统数字基带预失真系统的硬件成本和数值计算量。算法将传统算法中的复数乘法转换为极坐标中的幅度乘法和相位加法,使同样的计算步骤所消耗的乘法和加法次数分别降低了75%和50%。算法由通用的通带Volterra非线性模型进行推导得出,适用于当前的任意系统模型。对实际射频功放的测试实验结果验证了其有效性。     

功率放大器数字预失真技术的研究

在宽带码分多址(WCDMA)等宽带通信系统中,射频功率放大器呈现出严重的电记忆效应和热记忆效应,产生频谱再生和邻道干扰,传统的无记忆预失真技术已经无法消除信号失真而达到理想的线性化效果.针对此类有记忆性的功放,文章提出一种新的记忆多项式预失真器,以跟踪射频功率放大器特性的变化, 并进行非线性补偿.     

Behavioral modeling of RF power amplifiers based on pruned volterra series

Behavioral modeling techniques provide a convenient and efficient means to predict system-level performance without the computational complexity of full circuit simulation or physics-level analysis of nonlinear systems, thereby significantly speeding up the analysis process. General Volterra series based models have been successfully applied for radio frequency (RF) power amplifier (PA) behavioral modeling, but their high complexity tends to limit their applications to "weakly" nonlinear systems. To model a PA with strong nonlinearities and long memory effects, for example, the general Volterra model involves a great number of coefficients. In this letter, we propose a new simplified Volterra series based model for RF power amplifiers by employing a "near-diagonality" pruning algorithm to remove the coefficients which are very small, or else not sensitive to the output error, therefore dramatically reducing the complexity of the behavioral model.     

Chip for wideband digital predistortion RF power amplifierlinearisation

The authors present a custom chip for use in digital predistortion linearisation of RF power amplifiers. The chip is mainly implemented with systolic arrays. At maximum clock-rate, 130 MHz, the throughput is 16 Msamples/s with a 5 V supply voltage and power consumption of 1 W. A throughput of 2 Msamples/s is achieved at a 1.2 V supply voltage with 6 mW power consumption     

Peak‐to‐average power ratio reduction and digital predistortion effects in power amplifiers in OFDM system

In this paper, the effects of peak‐to‐average power ratio reduction in nonlinear power amplifiers (PAs) by considering memory effects and of digital predistortion are investigated. A new predistortion technique is proposed, which is called the complex gain memory predistortion (CGMP) method. The CGMP is applied to compensate the dynamic memory effects of PAs. The conventional partial transmit sequence method is applied for peak‐to‐average power ratio reduction, and combining it with the CGMP results in efficiency enhancement and spectrum efficiency improvement. Simulation and results are examined with the two types of PAs and with an OFDM signal with quadrature phase‐shift keying modulation. Copyright © 2011 John Wiley & Sons, Ltd.     

Optimization of EDGE terminal power amplifiers using memoryless digital predistortion

This paper describes a lookup-table (LUT)-based digital predistortion system usable for enhanced data for global system for mobile evolution (EDGE) handset transmitters. The system is memoryless and capable of improving average efficiency and performance in terms of the leakage power at offset frequencies and error vector magnitude. The obtainable efficiency at maximum linear output power is comparable, but at backoffs superior to commercial EDGE power amplifiers (PAs). Minimum system requirements on word length and LUT size have been investigated, which shows that a LUT having approximately 500 coefficients and a system word length of 13 bits are sufficient for EDGE. The proposed system is simple compared to basestation implementations comprising PA memory compensation and can be easily implemented in handsets in order to improve the overall system performance. The effects of antenna mismatch on system performance have been investigated     

一种高效的用于RF功率放大器线性化的自适应预失真结构

分析了当前文献中主要的几种自适应预失真结构,发现这些自适应预失真结构均不利于高效最小二乘算法的直接应用,从而限制了预失真技术的自适应性能.提出了一种新的自适应预失真结构,可直接使用高效的最小二乘算法对预失真器进行自适应更新.仿真结果表明利用此结构可快速、高效地实现非线性RF功率放大器的线性化.     

Distortion in polar modulated CMOS RF power amplifiers

Polar modulation of a switching RF amplifier is an excellent candidate to combine both linearity, efficiency and CMOS integration for RF power amplifiers used in mobile and wireless communication systems. In this paper, the different sources of distortion associated with polar modulation are discussed and verified by measurement results. A fully integrated linearized CMOS RF Power Amplifier for GSM–EDGE, realized in a 0.18 μm CMOS technology, is used as a benchmark to validate the presented theory. It is demonstrated how the combination of a differential delay between the amplitude signal and the phase signal, together with the AM–PM distortion of the Class E amplifier, generates an asymmetry in the output spectrum. The effect of low-pass filtering of the envelope signal is investigated and the degradation on the linearity with and without delay adjustment is given.     

Multi-order predistortion of power amplifiers using a second harmonic based technique

A novel multi-order predistortion linearizer is proposed to achieve independent control of the third- and fifth-order intermodulation products in high power amplifier. The approach is based on a combination of the second harmonic technique and the difference frequency technique. The second harmonic and difference frequency terms are generated using an envelope detector and two frequency multipliers. The RF predistorter has the advantage of low insertion loss and the requirement of a short delay line. Experimental results demonstrate an adjacent channel power ratio (ACPR) reduction of 11 dB for W-CDMA, at 2140 MHz.     

Design and optimization of CMOS RF power amplifiers

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-μm n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested     

InGaP HBT 大信号RF功率传输特性

本文实验研究了用于RF功率放大器的先进的InGaP HBT 器件大信号RF功率传输特性。研究了InGaP HBT在小信号和大信号状态下输出端的发射功率和反射功率及输入端的反射功率的规律。分析了InGaP HBT RF功率信号的多频率功率成份及其对大信号功率增益压缩,非线性和RF输出功率饱和的影响。     

Large signal RF power transmission characterization of InGaP HBT for RF power amplifiers

The large signal RF power transmission characteristics of an advanced InGaP HBT in an RF power amplifier are investigated and analyzed experimentally. The realistic RF powers reflected by the transistor, transmitted from the transistor and reflected by the load are investigated at small signal and large signal levels. The RF power multiple frequency components at the input and output ports are investigated at small signal and large signal levels, including their effects on RF power gain compression and nonlinearity. The results show that the RF power reflections are different between the output and input ports. At the input port the reflected power is not always proportional to input power level; at large power levels the reflected power becomes more serious than that at small signal levels, and there is a knee point at large power levels. The results also show the effects of the power multiple frequency components on RF amplification.     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.