一种高速低功耗ECL多模分频器的设计

本文介络一种高速低功耗ECL多模分频器的电路原理、电路和版图设计特点、工艺技术及研制结果。该分频器设计了0.5mA的内部开关电流和350mV的内部逻辑摆幅,输入输出均采用互补驱动。电路分频模数多,频率高,功耗低,典型功耗75mW,为相同集成度的普通ECL电路功耗的1/30～1/40。该电路广泛用于通讯、仪器仪表和频率合成器等领域。     

Algorithmic analogue-to-quaternary convertor circuit using current-mode CMOS

A new current-mode CMOS algorithmic analogue-to-quaternary data convertor circuit has been realised in a standard polysilicon-gate CMOS technology. This circuit accepts an analogue current input and develops a set of quaternary, base-four, output currents. A single type of convertor cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits.<>     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

Merged CMOS/bipolar current switch logic (MCSL)

A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-bit BiCMOS full adder was measured. This is about five times faster than an optimized CMOS adder.<>     

New constant-frequency multiresonant boost convertor

A new zero-voltage-switching multiresonant boost convertor operating at constant switching frequency is presented. Its output voltage is regulated by controlling the freewheeling period of the resonant inductor. It possesses the advantages of a PWM convertor and frequency-modulated multiresonant convertor. Moreover, by absorbing all major parasitic components in its resonant circuit, parasitic ringing is eliminated.<>     

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 μm L_eff, self-aligned TiSi₂ double-level metal, and an average minimum feature size of 1.35 μm. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

一种DC-DC开关电源片上软启动电路

提出了一种基于DAC(digital-to-analog converter)控制的数字软启动电路,利用DAC控制和软启动电压检测技术,有效抑制了DC-DC开关电源启动过程中产生的浪涌电流和输出电压过冲,实现了输出电压从零到调整值的平坦上升.在启动完成后启动电路的偏置电流被彻底关断,实现了低功耗没计.该软启动电路采用CMOS器件设计,无需任何外围元件,便于被DC-DC开关电源集成.该电路已成功集成到一款Buck型PWM(pulse width modulation)控制器当中,测试结果表明:在整个负载范围内,DC-DC在启动过程中电感电流平稳变化,输出电压平滑上升、无过冲,启动时间控制在1.2ms.     

High Power Factor Operation of a Three-Phase Rectifier for an Adjustable-Speed Drive

This paper presents a novel approach to improve the power factor (PF) and reduce the harmonics generated by an adjustable-speed drive (ASD). A high-frequency (HF) current injection technique is used to improve the PF and harmonic performance. The HF current at the same switching frequency (33 kHz) is injected into the input of a front-end rectifier from the output of an HF inverter. The main feature of the circuit is that it does not require any additional active devices for current injection. The inverter driving the induction motor is operated using a sinusoidal pulsewidth-modulation technique. The circuit simulation and experimental prototype results are presented for 67-hp (50 kW) and 3-hp three-phase induction motors, respectively.     

CMOS subnanosecond true-ECL output buffer

An emitter coupled logic (ECL) 100 K compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-ns delay) and sufficient precision are achieved through the use of a novel circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, and technology features, are shown. Measured and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented     

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (V_DD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s     

一种新型低噪声电流控制逻辑的分析与设计

本文绘出了一种新型电流控制逻辑的电路结构和工作原理，并由此提出了该逻辑的优化设计方法。通过采用恒定工作电流和限制电路的输出逻辑摆幅，电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。理论分析和电路模拟结果都表明，和静态CMOS电路相比，电流控制逻辑的峰值开关电流下降了近两个数量级．该逻辑可应用在高性能的模／数混合集成电路中。     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.     

双积分A/D转换器的量程自动转换

介绍了一种双积分式A/D转换器在宽范围量程测量中的自动量程转换技术.在测量仪表的输入通道中,用计数器对双积分型A/D转换器本身所固有的过量程/欠量程信号计数,计数器的输出作为量程编码去控制量程的选择,同时又是送到CPU的量程指示信号.该技术扩大了A/D转换量程,提高了精度,设计简单,工作可靠.     

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.     

Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC–DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC–DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC–DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC–DC converters operating at switching frequencies up to 10 MHz and above.     

A self-terminating low-voltage swing CMOS output driver

A CMOS output pad driver circuit is described that automatically series-terminates a driven line in the line's characteristic impedance. The circuit has advantages in speed, power, and size over conventional designs. The key idea is the use of emitter-coupled logic (ECL) compatible low-voltage swings for signaling, combined with the use of the driver transistor as both a switch and as a termination resistor. An on-chip measurement circuit dynamically adjusts the impedance of the driver to match the impedance of an external reference impedance standard, allowing the circuit to compensate for both chip and board level fabrication variations     

用CMOS工艺改善集成开关电容DC-DC变换器的特性

介绍了一种具有改进电路结构和改进工艺的单片集成3.3V/1.2V开关电容DC-DC变换器,其控制脉冲频率和固定导通比分别为10MHz和0.5.为了提高变换器的输出电流,采用CMOS工艺来制造电路中的开关器件和改进的互补型电路结构.使用Hspice电路仿真软件得到的仿真结果表明改进变换器的单个单元电路和互补型电路可使输出电流分别达到12.5mA和26mA,且后者的功率转换效率为73%,输出电压纹波小于1.5%.变换器在日本东京大学的标准Rohm 0.35μm CMOS工艺线上投片试制,测试结果显示,使用CMOS开关的变换器单元电路的输出电流为9.8mA.     

A dual differential bilateral current convertor

A simple differential input current convertor technique is described. The circuit offers separate input ports for differential voltage and current inputs, while generating a bilateral current output with minimum offset. High common-mode rejection is achieved without any critical component matching.