Single event transient effects on charge redistribution SAR ADCs

This work presents a study on the effects of Single Event Transients on Successive Approximation Register Analog-To-Digital Converters (ADC) based on charge redistribution. The effects of SETs are analyzed by means of an extensive fault injection campaign by using a SPICE simulator and a predictive 130nm CMOS technology model. Faults are injected in the analog blocks and in the digital control circuit of the converter. Results show that the transient effects may change the state of one or more bits of conversion, since the affected conversion stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Results also allow to identify the most sensitive nodes and the failure mechanisms associated to transient effects on this type of converter. Finally, some design-level mitigation strategies are applied, in a way that the error rate and the magnitude of conversion errors are significantly reduced.     

Single event transient pulse width measurement of 65-nm bulk CMOS circuits

Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.     

国产中高压抗辐照功率MOSFET单粒子效应

功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明：对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。     

Stable voltage reference sources

A family of well-regulated voltage references are shown, which are readily integrable for use with emitter-coupled logic, threshold logic, or linear circuit arrays. By relying on the relatively well-matched characteristics and the temperature tracking of integrated transistors and resistor ratios, the circuit can provide a large range of output fractions of the power supply. The relationships of the circuit components for various output voltages are derived. One circuit configuration gives fractions of the power supply of less than /SUP 1///SUB 2/ while another configuration gives fractions of the power supply greater than /SUP 1///SUB 2/. Limitations of the obtainable fractions are given. Experimental results are shown for each of the two basic circuit configurations and the temperature stability is demonstrated. Well-defined stable voltages are thus derived with a minimum of components and power drain.     

Single event upset and total dose radiation effects on rad-hard SRAMs

Radiation hardened 16K and 64K CMOS SRAMs were tested at the Brookhaven SEU Test Facility. No failures of 16K SRAMs were observed at room temperature with any value of the feedback resistors. SEU cross section measured at elevated temperatures was a function of reduced feedback resistance. A difference was observed in critical LET forBr andAu ions. SEU cross section decreased at very high angles of incidence. After initial SEU testing, the 64K SRAM was degraded by proton total dose irradiation. An increase in the SEU cross section as well as imprinting of the memory pattern was observed. Test chips fabricated by the same technology were also submitted to proton radiation. Threshold voltage shift was measured for NMOS transistors with and without inversion bias. An increase in the density of interface states for both NMOS and PMOS transistors was measured by the charge-pumping technique. This research has been supported by the NASA grants NAG-5-929 and NAG-9-333.     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

The impact of Miller and coupling effects on single event transient in logical circuits

With feature size scaling down, Miller feedback effects of gate-to-drain capacitance for transistors and coupling effects between interconnects will dramatically affect single event transient (SET) generation and propagation in combinational logic circuits. Two ways of ICs are arranged: linear and “S” types. For pulse width and delay time, SET propagations in two layouts of digital circuits are compared under considering the coupling effects between interconnects. An analytical model is used to describe the impact of Miller and coupling effects on SET propagation. A criterion for SET occurrence in digital circuits with effects of coupling and Miller feedback is presented. The influence of temperature and technology node on SET generation and propagation is analyzed. The results indicate that (1) the existence of these effects will improve the critical charge for SET generation and also reduce the estimated SER, and (2) the way of “S” type is more immune to SET than the scheme of linear.     

低压CMOS带隙电压源

介绍了CMOS带隙电压源的基本原理,并根据目前CMOS集成电路工艺发展对低电源电压的要求,详细地分析了几种能产生低输出电压且能兼容标准CMOS工艺的CMOS带隙电压源电路.这些电路所需的电源电压只有1V左右,并且都能够输出1V以下具有零温度系数的参考电压,其中有些电路的输出电压可以由电阻的比值来调节,因而可以增加电路设计的灵活性.本文还对低压CMOS带隙电压源电路的低频和高频噪声特性进行了深入分析,提出了改善输出参考电压噪声特性的途径.     

A ceramic-metal voltage reference tube

A glow discharge voltage reference tube constructed entirely of ceramic and metal has been developed. Minimum size (T2), extreme ruggedness, and unusual electrical stability characterize the tube. Operating voltage is approximately 85 v. Performance of the reference tube under conditions of shock, vibration, high temperature, and high altitude is described. Operating voltage stability over extended periods is demonstrated by presenting the results of precision measurements. Other aspects, such as temperature coefficient, ionization voltage, and the slope and smoothness of the voltage-current characteristic are discussed.     

A precision reference voltage source

With increasing temperature the base-emitter voltage of a transistor with a constant current decreases, while the difference in base-emitter voltages of two identical (integrated) transistors having a constant current ratio increases. From the sum of the two voltages a nearly temperature- independent output voltage is obtained if this sum equals the gap voltage of silicon. A reference voltage source of 10 V based on the principle is described. The reference part of the circuit is an integrated circuit, and thin-film resistors with a small relative temperature coefficient are used. An operational amplifier and a few resistors and capacitors complete the circuit. The source has a parabolic temperature characteristic and the temperature peak can be controlled by resistor adjustment. A change of /spl plusmn/10 K in respect of the peak temperature causes an output voltage change of -250 /spl mu/V, while a change of /spl plusmn/30 K causes a change of -2.2 mV. A long-term stability of 10 ppm/month was measured. The circuit can compete with the best available Zener diode sources, and has the added advantage that practically no selection is necessary.     

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm², a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming     

Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip

In this paper, experimental methods are emphatically described for measuring the proton single event effects (SEE) in Xilinx Zynq-7010 system-on chip. Experimental data are presented showing that low energy (3 MeV ≤ Energy ≤ 10 MeV) proton irradiation can cause single event effects in different hardware blocks of Xilinx Zynq-7010 SoC, including D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA). Moreover, the sensitivities of different hardware blocks to single event effects are different. Finally, the Stopping and Range of Ions in Matter (SRIM) software calculations show the possible reasons for this difference.     

Punchthrough transient voltage suppressor for low-voltageelectronics

Transient voltage suppressors for electronic circuits with power supply voltage of 3.3 V or lower are urgently needed but unavailable due to excessive leakage of low-voltage reversed p-n diodes. We analyzed several candidate device structures by using two-dimensional device simulation. Adopting the punchthrough mechanism in an n⁺p⁺p^-n⁺ structure rather than the traditional avalanche mechanism in a p⁺n⁺ structure, we can achieve low standoff voltage with excellent performances in low leakage current, low capacitance, and low clamping voltage. The new device appears to be satisfactory for protecting future electronic systems with power supply voltage at least down to 1.5 V     

Single event crosstalk prediction in nanometer technologies

As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-π model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.     

Bandgap voltage reference sources in CMOS technology

Two configurations are proposed for the implementation of bandgap reference sources in CMOS technology. The circuits presented are capable of high temperature operation, and allow a choice of the positive supply rail, the negative supply rail, or ground as the reference point.     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的栽流子迁移率和亚闽值斜率的温度系数。基于SMIC0．13μm的CMOS工艺的仿真结果表明,在-5-90℃的范围内。输出电压的温度系数为5ppm／℃。在室温时,整个电路能在低到0．9V的电源电压下工作并消耗0．68μW的功耗。     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的载流子迁移率和亚阈值斜率的温度系数.基于SMIC 0.13 μm的CMOS工艺的仿真结果表明,在温度为-55～90 ℃的范围内,输出电压的温度系数为5 ppm/℃.在室温时,整个电路能在低到0.9 V的电源电压下工作并消耗0.68 μW的功耗.     

Converter voltage reference performance improvement secrets

During the design process, many designers tend to examine each component separately. In mixed-signal design, however, in which different types of components are used, one must have a complete understanding of the individual components as well as their impact on and performance contribution to the overall system. When a design involves analog-to-digital converters (ADCs) or digital-to-analog converters (DACs), the analog signal buffer and the reference voltage source are as critical as is the converter selected. To achieve proper signal chain design, a deeper understanding of each component is necessary, and special care must be taken to consider the interaction between the different components and the respective impact on the overall system performance. With proper design and tuning of the signal chain, it is possible to preserve signal integrity and obtain the expected results.     

高性能带隙基准电压源的设计

本文基于带隙基准电压源的工作原理,实现了一种利用PATA电流产生基准电压的高性能带隙基准源。该带隙基准源温度特性良好,具有较高精度的输出电压,所以使电源管理芯片的工作电压具有更小的温度系数,使芯片工作更稳定。利用Candance仿真器,基于CSMCO．5umCMOSI艺对电路进行仿真,对基准源进行仿真与分析。仿真结果表明,当R2=316时,基准电压有最好的温度特性;并运用cadence软件中的“Calculator”工具计算出在该温度时,带隙基准电压源有最小的温漂系数。