Sliding mode audio class-D amplifier for portable devices

Audio class-D amplifiers are widely used in industrial and consumer portable electronic devices, such as mobile phones, thanks to their high efficiency. However, these amplifiers have a limited linearity due to their switching behavior and also a limited control bandwidth. To overcome these major drawbacks, this paper introduces a self-oscillating control technique based on the sliding mode theory which combines a large control bandwidth and a spread spectrum technique. A high power supply rejection, which is a crucial parameter in modules directly connected to a noisy battery, has also been achieved by introducing a variable hysteresis window. Theoretical analysis, behavioral and electrical simulations are discussed in detail in this paper. An integrated circuit using 0.13 μm CMOS process has been realized focused on mobile phone applications (0.8 W, 3.6 V and 8 Ω). The audio amplifier achieves 97 dB(A) signal-to-noise ratio, 0.02 % harmonic distortion and up to 80 dB of power supply rejection. The die area is smaller than 0.4 mm² while keeping more than 90 % efficiency at 1 W.     

数字音频D类功放电源误差校正方法研究

为了实时校正供电电源噪声引起的数字音频D类功放输出误差,提出一种基于FPGA的电源误差校正方法。使用高精度ADC芯片将电源纹波信号转化为数字量后送入FPGA,校正模块根据电源纹波的大小对数字音频D类功放Sigma-Delta调制器输入值进行预校正处理,从而实现在功放输出端有效的抑制电源噪声。经过实际电路测试,该方法可以有效的抑制电源噪声对数字音频D类功放的影响,电源抑制比达到36.78 dB。     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

一种高效率 PWM CMOS D类音频功率放大器

基于反馈系统的闭环结构,采用全差分前置放大和全差分反馈结构,提出了一种高效率PWM CMOS D类音频功率放大器,并采用一种具有滞回结构Rail-to-Rail比较器作为PWM比较器,以保证良好的噪声性能。整个电路基于CSMC 0.5μm CMOS工艺进行实现,最大转换效率达到90％,电源电压范围为2.5-5.5V,1kHz下的THD+N小于0.20％,电源抑制比为-75dB,空载消耗电流为2.8mA,待机电流为0.5μA,有效芯片面积为1.47mm*1.52mm,最大功率可以达到2.5W,能应用于各种高效率中小功率音频放大系统。     

A digital input class-D audio amplifier with sixth-order PWM

A digital input class-D audio amplifier with a sixth-order pulse-width modulation(PWM)modulator is presented.This modulator moves the PWM generator into the closed sigma–delta modulator loop.The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma–delta modulator.Therefore,at the output of the modulator,a very clean PWM signal is acquired for driving the power stage of the class-D amplifier.A sixth-order modulator is designed to balance the performance and the system clock speed.Fabricated in standard 0.18 m CMOS technology,this class-D amplifier achieves 110 dB dynamic range,100 dB signal-to-noise rate,and 0.0056%total harmonic distortion plus noise.     

一种应用于PWM D类音频功率放大器的CMOS Rail-to-Rail比较器

提出了一种应用于CMOS D类音频功率放大器的Rail-to-Rail PWM比较器,其输入级为Rail-to-Rail结构,输出级为AB类输出。基于CSMC 0.5μm CMOS工艺的BSIM3V3 Spice模型,采用Hspice对PWM比较器的特性进行了仿真,典型模型下的直流开环增益为50dB,电源抑制比为52dB,ICMR为0.04V~4.98V,传输时延为24.5ns,版图有效面积为210×75μm2。由于PWM比较器的良好性能参数,所以其不仅适用于D类音频功率放大器,也能应用于各类低频数据转换电路。     

New high-efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for portable consumer electronics

A single-chip of Class-D audio amplifier with high-power efficiency is presented. It includes a rectangular wave delta modulator (RWDM) and bridge-tied load output gate-drivers. The RWDM has a multiple inputs floating-gate hysteresis comparator and a feedback integrator formed by the external L-R low-pass filter. This monolithic Class-D audio amplifier with a maximum power efficiency of 92% has a flat frequency response with /spl plusmn/0.3 dB up to 20 kHz, and is capable of delivering up to 0.45 W of continuous average power into an 8-/spl Omega/ load at less than 0.5% total harmonic distortion plus noise from a 2.5-V power supply in the high fidelity range (20 Hz-20 kHz).     

A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Pulse density modulation (PDM) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in pulse width modulation based amplifiers. However, their low-voltage analog implementations also require a linear loop filter and a quantizer. A PDM based class-D audio amplifier using a frequency-domain quantization is presented. The digital intensive frequency-domain approach achieves high linearity under low supply regimes. An analog comparator and a single-bit quantizer are replaced with a current controlled oscillator (ICO) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, single-bit, class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18???m CMOS process with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-?? loudspeaker load. The amplifier can deliver the output power of 280 mW.     

Drive-transformerless class-D voltage-switching tuned power amplifier

Class-D voltage-switching tuned power amplifier circuits are presented, in which complementary pair transistors are used and bases of the transistors are coupled by a capacitor. These circuits have several advantages over previous circuits. They do not require a drive transformer and both transistors can be mounted on one heat sink.     

A 20-W stereo class-D audio output power stage in 0.6-/spl mu/m BCDMOS technology

This paper presents a highly power efficient 2/spl times/20-W class-D audio output power stage implemented in 0.6-/spl mu/m BCDMOS technology. The presented power stage is capable of driving 2/spl times/8-/spl Omega/ loads from a 20-V power supply at a power efficiency approaching 90%. Circuit details of thermal detection, over-current protection, and startup speaker click/pop are also presented. The performance of open-loop Class-D output stages are limited by the distortion mechanisms present within the power stage itself. A third-order PWM modulator was prototyped and used to dramatically improve the performance of the Class-D output stage by using feedback. The results of this work are also presented.     

A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma–delta ( $\Upsigma\Updelta$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD  ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.     

An integrated IF amplifier

An IF amplifier that provides a temperature insensitive Q (adjustable independently of center frequency) of 50 at a center frequency of f/SUB 0/ of 1 MHz, over a 100/spl deg/C temperature range is presented. The design also features supply independent biasing, input and output buffering, a 40-dB (automatic gain control) range and a center frequency voltage gain of up to 60 dB. Results obtained from computer simulations, discrete, and integrated prototypes are compared.     

Integrated overcurrent protection system for class-D audio power amplifiers

A fully integrated overcurrent protection system is presented suitable for application in integrated class-D audio power amplifiers. Accurate overcurrent detection is used based on parallel measurement of the voltage drop across the DMOS power transistors. A logic circuit enables continuous current limiting during overload situations. Actual short circuits can be distinguished from load impedance minima using a simple short-circuit discrimination method.     

2.2-W continuous-wave diffraction-limited monolithically integrated master oscillator power amplifier at 854 nm

A monolithically integrated master oscillator power amplifier (M-MOPA) with a flared power amplifier region operating at 854 nm has been fabricated that radiates in a single diffraction-limited lobe to an output power of 2.2-W continuous wave (CW). Additionally, the far field is extinguished by 26 dB with the master oscillator turned off enabling applications requiring digital modulation.     

An integrated class-B heating-aid amplifier

An integrated hearing-aid amplifier, which uses a new class-B output stage and operates from a single silver-oxide cell, is described. The amplifier has a voltage gain of 76 dB, a volume control range of 47 dB, and a quiescent current of approximately 90 /spl mu/A. It is shown that the average battery life cannot be significantly increased by a further reduction in quiescent current.     

音响放大器设计

针对传统音响放大的设计缺点,结合现代电子技术,采用音响放大集成电路,设计了一种音响放大器。首先分析了音响放大器的工作原理及电路组成,然后详细介绍了电源电路设计、电源整流、电源滤波;前置放大器设计;功率放大器设计;最后,分别对有效频率、总谐波失真、额定输出功率、输入阻抗、输出阻抗等主要技术指标进行了调试。调试结果表明,主要技术指标均达到设计要求,该设计具有较好的性价比,音响输出非常理想。     

CMOS RF class-D power amplifier with bandpass sigma-delta modulation

A CMOS radio frequency class-D amplifier is analysed and simulated with a bandpass ΣΔ modulated drive signal. The design includes a five stage driver and operates from 3.3 V. The simulated power efficiency at 181 MHz is 40.1% for a two tone source, and 16.6% for a 8.7 dB peak-to-average wideband code-division multiple access source signal. Equations are derived which demonstrate the relationship between amplifier load power, power efficiency, and modulator parameters called coding efficiency and average transition frequency.     

Broadband 60-W HF linear amplifier

The design, construction and performance of a solid-state untuned 2-30 MHz amplifier is described. Operation is from 28 V dc. Overall CW efficiency is greater than 47 percent at 60-w unfiltered output. Amplifier efficiency for two-tone 60-W PEP output is greater than 31 percent. two-tone linearity over the frequency range is -30 dB or better at output powers from 5-60 W. Broadband transmission-line transformers wound on ferrite toroids are used throughout for impedance matching. Hybrids of similar construction are used for output-power adding.     

Effect of dead time on harmonic distortion in class-D audio poweramplifiers

A model is described for predicting the harmonic levels introduced by the use of dead time in class-D, PWM-driven audio power output stages. The model demonstrates that the harmonic levels are a function of load impedance, modulation depth, dead time and switching frequency. In addition, measurements show that, for audio applications, dead time is the dominant cause of power stage nonlinearity     

高保真音频功放器设计

针对高品质音频的需求,设计了一种高保真音频放大器。该音频放大器主要由信号放大电路、功率放大电路和有源滤波电路组成,其中信号放大部分采用场效应管及运算放大器。其受外界的干扰性较小,稳定性较高,放大倍数可达到20～30倍,随需要而进行调节。功放部分采用LM4766型芯片,采用差动放大电路对信号实现音频信号的放大,失真小于百分之零点一。滤波电路采用了二阶有源低通滤波电路,对输入的音频信号进行处理。该设计的音频功率放大器具有失真度小、增益可调、体积小等特点,具有较高的实用价值。