Unified subharmonic oscillation conditions for peak or average current mode control

This paper is an extension of the author's recent research in which only buck converters were analyzed. Similar analysis can be equally applied to other types of converters. In this paper, a unified model is proposed for buck, boost, and buck–boost converters under peak or average current mode control to predict the occurrence of subharmonic oscillation. Based on the unified model, the associated stability conditions are derived in closed forms. The same stability condition can be applied to buck, boost, and buck–boost converters. Based on the closed‐form conditions, the effects of various converter parameters including the compensator poles and zeros on the stability can be clearly seen, and these parameters can be consolidated into a few ones. High‐order compensators such as type‐II and PI compensators are considered. Some new plots are also proposed for design purpose to avoid the instability. The instability is found to be associated with large crossover frequency. A conservative stability condition, agreed with the past research, is derived. The effect of the voltage loop ripple on the instability is also analyzed. Copyright © 2014 John Wiley & Sons, Ltd.     

Fast‐scale stability limits of a two‐stage boost power converter

There are many applications in power electronics that demand high step‐up conversion ratio between the source and the load. A simple way of achieving such a high voltage ratio is by cascading DC–DC boost converters in a few stages. The individual converters in such a cascaded system are usually designed separately applying classical design criteria. This paper investigates the stability of the overall system of a cascade connection of two boost converters under current mode control. We first demonstrate the bifurcation behavior of the system, and it is shown that the desired periodic orbit can undergo fast‐scale period doubling bifurcation leading to subharmonic oscillations and chaotic regimes under parameter variation. The value of the intermediate capacitor is taken as a design parameter, and we determine the minimum ramp slope in the first stage required to maintain stability. It is shown that smaller capacitance values give rise to wider stability range. We explain the bifurcation phenomena using a full‐order model. Then, in order to simplify the analysis and to obtain a closed‐form expression to explain the previous observation, we develop a reduced‐order model by treating the second stage as a current sink. This allows us to obtain design‐oriented stability boundaries in the parameter space by taking into account slope interactions between the state variables in the two stages. Copyright © 2015 John Wiley & Sons, Ltd.     

Analytical multi‐parametric stability boundaries of DC‐DC buck converters under V1 control concept

Two main methods for controlling switching converters exist in the literature. The direct one is the voltage mode control, which suffers from some disadvantages such as slow response to load variations and an input voltage‐dependent total loop gain. The current mode control can overcome these problems but at the expense of extra cost and more complex control design. V¹ concept is a new promising control technique for designing voltage mode control of buck‐type converters with an optimal response similar to current mode control. In this paper, the dynamics and the stability of buck converters under V¹ control are studied. In particular, subharmonic oscillation limits in the parameter space are addressed. First, a closed‐loop state‐space model is derived and then used to formulate an analytical matrix‐form expression for predicting the stability limit of the system. Using this expression, multi‐parametric stability boundaries are obtained. It is shown that the equivalent series inductance of the output capacitor can narrow the stability region. It is also demonstrated that the integral action in the feedback loop of a V¹‐controlled buck converter has a negligible effect on the subharmonic oscillation boundary. The theoretical analysis is validated through numerical simulation of the circuit‐level switched model of the system. Copyright © 2017 John Wiley & Sons, Ltd.     

Graph‐theoretical approach to 2‐switch DC–DC converters

This paper presents a graph‐theoretic approach to analyse and synthesize switch mode DC–DC converters. The result is based on the state‐space averaging equation and the fundamental graph theory. Hence our proposed method is applied to various kinds of DC–DC converters with two switches and topological conditions for two‐switch DC–DC converters are obtained systematically. Copyright © 2005 John Wiley & Sons, Ltd.     

Exact sampled‐data analysis of quasi‐resonant converters with finite filter inductance and capacitance

Previous models of quasi‐resonant converters generally use averaging and assume infinite filter inductance and capacitance to reduce circuit complexity, but at the expense of accuracy. In this paper, exact sampled‐data modelling is used. A general block diagram model applicable to various topologies of quasi‐resonant converters is proposed. Large‐signal analysis, steady‐state analysis and small‐signal analysis are all studied. They agree closely with the experimental results in the literature. Compared with the averaging approach, the sampled‐data approach is more systematic and accurate. Copyright © 2001 John Wiley & Sons, Ltd.     

Dynamics of PFC power converters subject to time‐delayed feedback control

Power factor correction converters are power electronics circuits used as AC‐DC power supplies. These systems are well known to exhibit nonlinear phenomena such as subharmonic oscillations and chaotic regimes. These undesirable behaviors increase the THD and therefore can jeopardize enormously the system performances. In this paper, time delay feedback control is applied to stabilize a two‐stage power factor correction AC‐DC converter when it exhibits these instabilities under traditional controllers. This control technique introduces many advantages to the most and widely used average current mode control through widening the stability domain of the system. By appropriately selecting the time delay feedback gain and the time delay period, the undesirable subharmonic components are eliminated, whereas the desired ones remain unchanged. A harmonic balance approach is used for studying the dynamics of the system under the new control scheme and to obtain the stabilization domain. Copyright © 2010 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

Non‐isolated single‐switch DC–DC converters with extended duty cycle for high step‐down voltage applications

Several new topologies of single‐switch non‐isolated DC–DC converters with wide conversion gain and reduced semiconductor voltage stress are proposed in this paper. Most of the proposed topologies are derived from the conventional inverse of SEPIC (Zeta) converter. The proposed topologies can operate with larger switch duty cycles compared with the existing single switch topologies, hence, making them well suitable for high step‐down voltage conversion applications. With extended duty cycle, the current stress in the active power switch is reduced, leading to a significant improvement of the system losses. Moreover, the active power switch in some of the proposed topologies is utilized much better compared to the conventional Zeta and quadratic‐buck converters. The principle of operation, theoretical analysis, and comparison of circuit performances with other step‐down converters are discussed regarding voltage and current stress and switch silicon utilization. Finally, simulation and experimental results for a design example of a 50 W/5 V at 42‐V input voltage operating at 50 kHz will be provided to evaluate the performance of the proposed converters. Copyright © 2014 John Wiley & Sons, Ltd.     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Steady‐state stability of shaft torsional oscillation in an ac‐dc interconnected system with self‐commutated converters

Recent progress in power electronics technology makes it possible to consider applying self‐commutated converters using gate turn‐off thyristors (GTOs) to HVDC transmission systems. Since the self‐commutated converter can be operated stably without depending on ac‐side voltage, the magnitude and the phase angle of the converter output voltage can be controlled independently. Therefore, this type of converter will improve voltage stability at its ac side. On the other hand, shaft torsional oscillation of a thermal power plant caused by the interaction between the shaft‐generator system and the control system of the self‐commutated converter is still an open problem. In this paper, a linearized model for eigenvalue analysis of a power system, including HVDC interconnection with self‐commutated converters, is described to analyze the effect of the self‐commutated converter on the shaft torsional oscillation of a thermal power plant. Then, numerical results from the eigenvalue analysis of the shaft torsional oscillation are presented. Results obtained by the frequency response method are also reported. The numerical results make it clear that parameter regions of DC‐AVR and ACR control systems of self‐commutated converters exist where the shaft torsional oscillation may be caused. © 1999 Scripta Technica, Electr Eng Jpn, 128(4): 25–37, 1999     

Poles–zeros analysis and broadband equivalent circuit for on‐chip spiral inductors

Poles and zeros of the transfer function determine the performance and the key features of the circuit network, such as phase, gain, and bandwidth. In this paper, the contribution of the poles and zeros to the transfer function has been shown. The factors η_p and η_z are proposed to account for the poles contribution to the peak and the zeros contribution to the valley of transfer function, respectively. A novel broadband equivalent circuit combining the physics‐based circuit model and behavioral macro‐model (black‐box) network is proposed for accurately characterizing on‐chip spiral inductors. The physics‐based elements are extracted using the linear dependence of a set of characteristic functions on variables (such as ω²) or other functions in a certain frequency range. The macro‐model network described by rational functions is determined using vector fitting approaches. The proposed modeling method is validated by the on‐chip spiral inductor fabricated with 0.13‐µm SiGe BiCMOS aluminum process. Excellent agreements are obtained between the measured data and calculation for the proposed model up to 40 GHz. Copyright © 2015 John Wiley & Sons, Ltd.     

A systematic approach to designing a wide‐current range,MOS capacitor‐based switched‐capacitor DC‐DC converter with an augmenting LDO

Switched‐capacitor DC‐DC converters (SC DC‐DC) are analyzed for loss sources, voltage regulation integrity, start‐up latency, and ripple size, while the trade‐offs between these metrics are derived. These analyses are used to design a SC DC‐DC that achieves high efficiency in a wide load current range. Four‐way interleaving was employed to reduce the output ripple and efficiency loss due to this ripple. The design can be reconfigured to achieve gains of 1/3 and 2/5 for inputs ranging between 1.4 and 3.6 V to generate output voltage range of 0.4 to 1.27 V and can supply peak load current of 22 mA. It uses thin‐oxide MOS capacitors for their high density and achieves 75.4% peak efficiency with an input frequency of 100 MHz and a load capacitor of 10 nF. An augmenting LDO that only regulates during sudden load transients helps the converter respond fast to these transients. The chip was implemented using a 65‐nm standard CMOS process.     

Modeling of switching frequency instabilities in buck‐based DC–AC H‐bridge inverters

In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period‐doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete‐time model able to predict both instability phenomena is derived. The model is obtained without making the quasi‐static approximation and it can be used to obtain the useful operation region in the multi‐dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. Copyright © 2010 John Wiley & Sons, Ltd.     

计及换流器间动态交互的中压直流配电系统控制参数设计

由于各换流器间存在动态交互作用,使得中压直流(MVDC)配电系统的控制参数设计比单台换流器时困难得多。首先,针对系统中换流器的电流控制环、电压控制环和下垂控制环,依次分别建立了计及换流器间动态交互的开环和闭环传递函数,并且所建传递函数零极点的个数与单台换流器独立运行时完全一致。然后,提出了一种计及换流器间动态交互的MVDC配电系统控制参数设计方法,该方法能够从系统动态稳定性的角度定性定量设计控制参数。该设计方法通过部分零极点的相互抵消,利用一对共轭主导极点准确设计系统动态特性,并在较宽频率范围(如10~50 Hz)内均有效。最后,在电力电子仿真软件PLECS中对所提传递函数和控制参数设计方法进行了仿真验证。     

Data‐Driven Controller Tuning for Nonminimum Phase Plants with Stability Constraints

This paper addresses the model reference control problem, which is a typical control problem found in data‐driven controller tuning methods. For nonminimum phase plants, the unstable zeros of the plant should be included in the reference to avoid destabilization of the resulting closed‐loop system and improve tracking performance. First, we propose a data‐driven controller tuning method with closed‐loop stability taken into consideration and with the tuned controller parameters in the time domain. If the plant has unstable zero(s), the proposed method would not lead to destabilizing controller in the worst case. Closed‐loop stability is checked using linear inequalities described with input/output data. This contributes to reducing computation in the proposed method. Moreover, this paper proposes a data‐driven controller tuning method for nonminimum phase plants estimating the unstable zero(s) using a flexible reference model at each parameter update and reflecting them into the resulting reference model. The effectiveness of the proposed method is confirmed through numerical experiments.     

计及换流器间动态交互的中压直流配电系统控制参数设计

由于各换流器间存在动态交互作用,使得中压直流(MVDC)配电系统的控制参数设计比单台换流器时困难得多。首先,针对系统中换流器的电流控制环、电压控制环和下垂控制环,依次分别建立了计及换流器间动态交互的开环和闭环传递函数,并且所建传递函数零极点的个数与单台换流器独立运行时完全一致。然后,提出了一种计及换流器间动态交互的MVDC配电系统控制参数设计方法,该方法能够从系统动态稳定性的角度定性定量设计控制参数。该设计方法通过部分零极点的相互抵消,利用一对共轭主导极点准确设计系统动态特性,并在较宽频率范围(如10~50 Hz)内均有效。最后,在电力电子仿真软件PLECS中对所提传递函数和控制参数设计方法进行了仿真验证。     

Nonaveraged control‐oriented modeling and relative stability analysis of DC‐DC switching converters

This paper presents a unified and exact nonaveraged approach to derive a frequency‐domain control‐oriented model for accurate prediction of the fast timescale dynamics and performances of switching converters with fixed frequency naturally sampled pulse width modulation and integrating feedback loop. Because the approach avoids averaging and approximations related to this process, a very good accuracy of the derived model is obtained. The main difference between the presented approach and the existing methodology for accurately predicting the behavior of switching converters is that, here, we break the feedback loop and we focus on analyzing the open‐loop gain and the effect of the system parameters on relative stability. This results in an approach much similar to control systems techniques rather than nonlinear dynamical system approaches. Consequently, the relative stability is tackled easily in the frequency domain. In particular, by treating the modulator as a gain depending on the operating point, the new model is formulated in such a way that standard control‐oriented tools such as Bode diagrams and root‐loci can be easily used. Therefore, the proposed approach gives some important issues like gain and phase margins that are highly useful in controller design. It is noticed that the crossover frequency, gain, and phase margins predicted by using the averaged model may deviate significantly from the actual values given by the proposed approach. The paper points out the sources of discrepancies and the theoretical results are validated by simulations using a circuit‐level switched model.     

Reliability challenge for impedance network‐based DC‐DC boost converters

In this paper, reliability evaluation is proposed for some of the most famous impedance network‐based DC‐DC boost converters. Markov reliability approach is used to evaluate the reliability of the converters. Also, some other factors such as components' failure rates, reliability functions, and mean time to failures are introduced and evaluated. Detailed explanations for the evaluation methods of the mentioned factors are also provided in the context of the paper. In addition to the mathematical analysis, numerical calculations are also done through the simulation results of the converters. Simulations are done in PSCAD/EMTDC. Finally, a numerical and graphical reliability comparison is provided for the mentioned converters. The purpose of this paper is to give a comprehensive reliability evaluation and comparison for some of the most popular impedance network‐based DC‐DC converters. In addition, this paper gives a detailed reliability analysis that can be used in reliability assessment of all types of power electronic converters, so it can help the researchers to consider reliability calculations into their designing.     

MTL‐based implementation of current‐mode CMOS RMS‐to‐DC converters

In this paper, systematic implementation of current‐mode RMS‐to‐DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC‐based RMS‐to‐DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square‐root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi‐purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS‐to‐DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square‐rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 µm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.     

Transient analysis of multi‐state dc–dc converters using system energy characteristics

The study of multi‐state dc–dc power conversion techniques is restricted by the complicated inner switching behaviors. This paper presents a general and unified transient analysis for various sorts of multi‐state dc–dc converters from a viewpoint of their system energy characteristics. With the applications to the boost converters, the proposed analytical method has indicated its advantages of high convenience and practicability to the multi‐state converters. The generalized concepts of system energy parameters of dc–dc converters are introduced and applied to the transient analysis. Consequently, the expressions of system model parameters of multi‐state dc–dc converters are deduced. The new 2nd order transfer functions are obtained to describe the large‐ and small‐signal mathematical models accurately. The model simulation and experimental results are provided to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.