Memristor‐based voltage‐controlled relaxation oscillators

This paper introduces two voltage‐controlled memristor‐based reactance‐less oscillators with analytical and circuit simulations. Two different topologies which are R‐M and M‐R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor‐based voltage‐controlled oscillator (VCO) is introduced as an application for the proposed circuits which is nano‐size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Optimum design of high power and high efficiency mm‐wave fundamental oscillators

A systematic method to design high power and high efficiency mm‐wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77‐GHz two‐stage (differential) VCO is designed in a 65‐nm CMOS process. Careful electromagnetic and circuit simulations demonstrate that the designed VCO has 2‐GHz tuning range, maximum output power of 10.5 dBm and maximum DC to RF efficiency of 24.1%. The designed VCO shows 54.8% and 108.7% improvement in terms of maximum output power and efficiency compared with a conventional cross‐coupled VCO with the same tuning range.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

Time‐domain analysis of phase‐noise and jitter in oscillators due to white and colored noise sources

This paper presents an original time‐domain analysis of the phase‐diffusion process, which occurs in oscillators due to the presence of white and colored noise sources. It is shown that the method supplies realistic quantitative predictions of phase‐noise and jitter and provides useful design‐oriented closed‐form expressions of such phenomena. Analytical expressions and numerical simulations are verified through measurements performed on a relaxation oscillator whose behavior is perturbed by externally controlled noise sources. Copyright © 2011 John Wiley & Sons, Ltd.     

A generalized family of memristor‐based voltage controlled relaxation oscillator

Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage‐controlled memristor‐based relaxation oscillator including two memristors is presented. The operation of two memristors‐based voltage relaxation oscillator circuits is demonstrated theoretically with the mathematical analysis and with numerical simulations. The generalized expressions for the oscillation frequency and conditions are derived for different cases, where a closed form is introduced for each case. The effect of changing the circuit parameters on the oscillation frequency and conditions is investigated numerically. In addition, the derived equations are verified using several transient PSPICE simulations. The power consumption of each oscillator is obtained numerically and compared with its PSPICE counterpart. Furthermore, controlling the memristive oscillator with a voltage grants the design an extra degree of freedom which increases the design flexibility. The nonlinear exponential model of memristor is employed to prove the oscillation concept. As an application, two examples of voltage‐controlled memristor‐based relaxation oscillator are provided to elaborate the effect of the reference voltage on the output voltage. This voltage‐controlled memristor‐based relaxation oscillator has nano size with storage property that makes it more efficient compared with the conventional one. It would be helpful in many communication applications.     

New structures of four‐phase oscillators obtained by strongly interweaving mono‐phase limit‐cycle oscillators

The present work is a part of our effort of developing multiphase oscillators. The particular system dealt with here is that of strongly nonlinearly coupled four oscillators that form a multiphase source. Such sources possess potential applications in power electronics, in phased‐array antennas, and in modern methods of modulation and especially in demodulating multi‐phased modulated signals. The present system can be interpreted as embracing four two‐phase oscillators. Nevertheless, as a result of the strong coupling, the second state equation of each oscillator merges with the first equation of the following oscillator. The resulted four‐phase source is, therefore, represented by merely four state equations. The applications related to communications (especially those related to receivers) may be susceptible to the noise performance of the source. We believe that the presently suggested system, which relies on strong coupling of oscillators, is advantageous in its noise performance in comparison to more straightforward recently described multiphase sources, which incorporate loosely coupled oscillators. Copyright © 2007 John Wiley & Sons, Ltd.     

A family of memristor‐based reactance‐less oscillators

In this paper, we present for the first time a family of memristor‐based reactance‐less oscillators (MRLOs). The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the ‘resistance storage’ property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented. Copyright © 2013 John Wiley & Sons, Ltd.     

Phase error analysis in CMOS injection‐coupled LC quadrature oscillator (IC‐QO)

This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators (QOs). Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

An inductorless CMOS quadrature oscillator continuously tuneable from 3.1 to 10.6 GHz

Modern RF front‐ends require wide tuning‐range oscillators with quadrature outputs. In this paper we present a two‐integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013mm², leading to a figure‐of‐merit FOMA of ?176.7dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency. Copyright © 2010 John Wiley & Sons, Ltd.     

Sinusoidal shaping of the ISF in LC oscillators

A new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of ?130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on‐chip spiral inductor with a quality factor equal to 8. Copyright © 2007 John Wiley & Sons, Ltd.     

Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

A 5‐MHz AT‐cut quartz crystal oscillating circuit functioning in 350 nA

An oscillating circuit functioning at ultra low power (350 nA) for a 5‐MHz AT‐cut quartz crystal oscillator was investigated. This circuit has a resistance between the power terminal of the CMOS‐IC and the power supply, and another between the earth terminal of the CMOS‐IC and the ground (GND). These resistances discourage an inrush of current, and set a gain (g_m) necessary for oscillating the circuit at minimum. The developed circuit is quite simple, but enables driving at once‐unthinkable, low power (below 1 µA). © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Mixed‐mode analysis of the sensitivity of a radiofrequency oscillator disturbed by parasitic signals

The first step of this work is to study the susceptibility of a radiofrequency oscillator to deterministic disturbance sources. A Colpitts oscillator, working around a 4 GHz frequency, contains a heterojunction bipolar transistor with a silicon–germanium base as an active device. A mixed‐mode analysis is involved, applying a microscopic drift diffusion model to the device, whereas the rest of the circuit used is governed by Kirchhoff's laws. We assume that this tool is very relevant to grasp the influence of intrinsic or extrinsic noisy sources of the oscillator. Our first simulation raw results motivate us to discuss, and perhaps extend, via some analytical models, the so‐called impulse sensitivity function model. In this paper, we try to develop quantitative predictions about the phase noise of such oscillators, and to give some new tracks on this field. Copyright © 2008 John Wiley & Sons, Ltd.     

A wide variable‐range CMOS–VCXO for IC

Recently, miniaturization, low power consumption, and high‐frequency stability have been required in crystal oscillators as a frequency source, because of the rapid development of mobile communications, typified by cellular phones. Usually, a VCXO (Voltage Controlled Crystal Oscillator) has been included in PLL. And it has been required that the VCXO should be implemented on a CMOS–IC chip. The oscillating frequency of a traditional VCXO has been controlled by capacitance variation of a varactor diode. But it is difficult to implement the varactor diode on an IC chip. In our previous study, we showed that a transistor VCXO utilizing the MOSFET's Miller capacitance of a variable capacitance circuit had a wide frequency variable range. On the other hand, in a CMOS–VCXO, the Miller capacitance has decreased. Therefore, a wide frequency variable range could not be obtained by utilizing the Miller capacitance in the CMOS–VCXO. In this paper, first, a variable capacitance circuit is realized in order to construct a wide‐variable‐range CMOS–VCXO for IC. The variable capacitance circuit is composed of a MOSFET as a voltage controlled resistance. Next, the CMOS–VCXO is constructed by the variable capacitance circuit and a CMOS crystal oscillator. As a result, we show that the CMOS–VCXO has a wide frequency variable range of about 400 ppm.© 1999 Scripta Technica, Electr Eng Jpn, 130(3): 49–56, 2000     

A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

Phase noise analysis in CMOS differential Armstrong oscillator topology

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano‐scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Resistive‐less memcapacitor‐based relaxation oscillator

Recently, the realization of the conventional relaxation oscillators was introduced based on memristors. This paper validates the concept using two series memcapacitors in general which is applicable for a capacitor and memcapacitor as well. Furthermore, the necessary conditions for oscillation are introduced, and a generalized closed‐form expression for the oscillation frequency is derived. Two special cases are introduced and verified using PSPICE simulations showing a perfect matching. Copyright © 2014 John Wiley & Sons, Ltd.