Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.     

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

Impact of parasitics on even symmetric split‐capacitor arrays

This paper analyzes the impact of parasitic capacitances in the performance of split capacitive‐based digital‐to‐analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the main responsible for the nonlinear behavior of these arrays, particularly for low‐to‐medium resolution converters. In order to validate the analysis, two versions of a complete low‐power, low‐voltage successive‐approximation register analog‐to‐digital converter (ADC), intended for a disposable multi‐channel bio‐medical monitoring system, have been fabricated in a 0.35 µm standard complementary metal‐oxide‐semiconductor technology. The only difference between these two prototypes is that in one of them, the capacitive array is surrounded by dummy capacitors, while in the other prototype is not. Hence, the former achieves better mismatch performance at the expense of increased parasitics. The experimental results demonstrate that the version without dummy capacitors obtains higher effective resolution than the ADC with dummies, the power consumption being essentially the same for both prototypes, namely: 130nW at 2kS/s from a 1‐V supply. These results are in full agreement with the analysis reported in the paper and confirm the proposed sizing procedure. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Self‐calibrated SAR ADC based on split capacitor DAC without the use of fractional‐value capacitor

A successive approximation register analog‐to‐digital converter (SAR ADC) based on a split‐capacitor digital‐to‐analog converter (CDAC) with a split binary weighted capacitor array and C‐2C ladder is proposed. In present design, a unit split capacitor is used in the CDAC instead of the fractional‐value capacitor in the conventional configuration. The preset error induced by the unit split capacitor and the mismatch error of the upper bit CDAC are self‐calibrated. The calibration range and the impact of calibration DAC resolution on circuit linearity are studied to provide an optimum design guideline. Behavior simulation and post‐layout simulation are performed to verify the proposed calibration method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 9‐bit successive approximation ADC in SOI CMOS operating up to 300 °C

Industrial electronics are in great demand for oil and gas exploration, well drilling, and automotive applications where the operating temperature goes beyond 200 °C. Circuit designs using conventional complementary metal–oxide semiconductor (CMOS) technology are mostly rated at maximum of 125 °C, which is not suitable for harsh environment. In this paper, a high‐temperature (HT) 9‐bit successive approximation register analog‐to‐digital converter (SAR ADC) designed in silicon‐on‐insolation CMOS technology with a sampling rate of 50 kS/s is presented. The design considerations of the HT SAR ADC are discussed from process selection, temperature‐aware circuit design, and measurement perspectives. The ADC achieves an effective number of bit (ENOB) of 8.35 bits and a figure of merit of 93 pJ/step at room temperature. Under HT test, ENOBs of 7.3 bits at 225 °C and 6.9 bits at 300 °C are obtained. The power consumption is 1.52 mW from a 5‐V supply at room temperature and only 2.17 mW at 300 °C. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.     

FFT‐based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform (FFT)‐based digital calibration method for 1.5 bit/stage pipeline analog‐to‐digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non‐ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low‐gain OPAMP can be used in high‐performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal‐to‐noise‐and‐distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

A low‐power small‐area 10‐bit analog‐to‐digital converter for neural recording applications

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog‐to‐digital converters (ADCs). A time‐based approach is used for the subtraction and amplification in conjunction with a current‐mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog‐to‐digital conversion. Based on introduced structure, a 10‐bit 100‐kSample/s time‐based cyclical ADC has been designed and simulated in a standard 90‐nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system‐level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal‐to‐noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of ?64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280µm × 250µm. The total power dissipation is 5µW per conversion stage and 20µW from an 1.2‐V supply for full‐scale conversion. Copyright © 2010 John Wiley & Sons, Ltd.     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

Application of duality principle to synthesis of single‐stage power‐factor‐correction voltage regulators

The duality principle is applied to derive new single‐stage power‐factor‐correction (PFC) voltage regulators. This paper begins with an application of duality transformation to conventional discontinuous‐conduction‐mode buck, buck‐boost and boost converters. The resulting dual converters operate in the discontinuous capacitor voltage mode. These new converters provide the same PFC property, but in the dual manner. It is proved that in the practical case of the input being a voltage source, the mandatory insertion of inductance between the voltage input and the ‘dual PFC converter’ does not affect the power‐factor‐correcting property. A new single‐stage PFC regulator is derived by taking the dual of a well‐known circuit based on a cascade of conventional boost and buck converters. Analytical design expressions are derived, illustrating the relation between current stress and component values. Experiments are performed to confirm the operation of the circuit and its power‐factor‐correcting capability. Copyright © 2003 John Wiley & Sons, Ltd.     

Dynamic modeling of a dual active bridge DC to DC converter with average current control and load‐current feed‐forward

Bidirectional power flow is needed in many power conversion systems like energy storage systems, regeneration systems, power converters for improvement of the power quality and some DC‐DC applications where bidirectional high power conversion and galvanic isolation are required. The dual active bridge (DAB) is an isolated, high voltage ratio DC‐DC converter suitable for high power density and high power applications, being a key interface between renewable energy sources and energy storage devices. This paper is focused on the modeling and control design of a DC‐DC system with battery storage based on a DAB converter with average current mode control of the output current and output voltage control. The dynamic response of the output voltage to load steps is improved by means of an additional load‐current feed‐forward control loop. An analytical study of the load‐current feed‐forward is presented and validated by means of both simulations and experimental results. Copyright © 2014 John Wiley & Sons, Ltd.     

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.     

High‐power‐factor single‐switch AC to DC converter for LED lighting

In this paper, we report a novel single‐switch AC to DC step‐down converter suitable for light emitting diodes. The proposed topology has a buck and a buck–boost converter. The circuit is designed to operate in the discontinuous conduction mode in order to improve the power factor. In this topology, a part of the input power is connected to the load directly. This feature of the proposed topology increases the efficiency of power conversion, improves the input power factor, produces less voltage stress on intermediate stages, and reduces the output voltage in the absence of a step‐down transformer. The theoretical analysis, design procedure, and performance of the proposed converter are verified by simulation and experiment. A 36 V, 60 W prototype has been built to demonstrate the merits of this circuit. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Analysis and design of a dual‐mode control flyback converter

This letter presents a dual‐mode control scheme to improve the efficiency of a flyback converter in a wide load range. The proposed flyback converter features a novel dual‐mode operation. The valley‐switching technique is adopted to reduce the switching loss at light load. On the other hand, the fixed off‐time (FOT) controls with continuous conduction mode operations decrease the conduction losses at heavy load. The principles and design procedures of the proposed dual‐mode controller are discussed and analyzed. Finally, a 140‐W dual‐mode flyback converter with an output voltage of 19 V is implemented. Experimental results agree with the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

An Approach to a Higher‐Power‐Density Power Supply for a 380‐V DC Distribution System

A methodology for realizing a higher‐power‐density DC‐DC converter has been proposed for a power unit installed in a 380‐V DC distribution system. The possibility of the converter design will be strengthened by using the series–parallel connection topology for isolated DC‐DC converters. A converter prototype with a power density of 10 W/cm³ has been fabricated, and the feasibility of the converter design has been confirmed experimentally. This result contributes to the realization of a highly efficient and highly space‐saving 380‐V DC distribution system. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(3): 51–62, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22494