Frequency–amplitude relations for cross‐coupled voltage‐controlled oscillator

Dependence of frequency on amplitude and control bias is considered for the cross‐coupled voltage‐controlled oscillator. Closed form expressions are derived for frequency of oscillation as a function of amplitude, for positive and negative control bias voltages. Theory of nonlinear ordinary differential equations is utilized to show that the capacitance–voltage relation is the main cause of frequency shift with amplitude. Furthermore, the case of small amplitudes relative to control voltage is analyzed, and a closed form expression is derived for dependence of frequency on amplitude. This relation is then verified using the concept of effective capacitance. The effective capacitance approach is also used to extend the analysis to large voltage swings. Dependence of frequency on tuner control voltage is calculated for both bias polarities. Implications of the aforementioned equations for voltage‐controlled oscillator performance are discussed. Numerical calculations and simulations are used to compare and verify the closed form equations, showing good agreement. Copyright © 2012 John Wiley & Sons, Ltd.     

Crosstalk cancelling voltage‐mode driver for multi‐Gbps parallel DRAM interface

For multi‐Gb/s/pin parallel dynamic random access memory (DRAM) interface, a crosstalk cancelling voltage‐mode driver is proposed. The voltage‐mode driver is composed of a main driver and sub‐drivers where the cancellation signal is generated by the sub‐drivers. The outputs of the main driver and sub‐drivers are combined by a capacitive coupling so the direct current (DC) output swing is not affected by the crosstalk cancellation and the sub‐drivers may not consume DC power. The proposed crosstalk cancelling voltage‐mode driver implemented in a 0.11‐µm complementary metal‐oxide semiconductor (CMOS) technology improves the horizontal eye openings by 22.6 ps at 4‐Gbps/pin. Copyright © 2014 John Wiley & Sons, Ltd.     

Dynamic C‐V characteristic for a varactor load connected with a transmission line

Crosstalk is induced by a reflected wave of a load connected with a transmission line. Thus, analysis of the reflected wave is important. The reflected wave generated from a nonlinear load is complicated. In order to estimate the complicated reflected wave, we measured the reflected and incident waves for the nonlinear load and estimated the dynamic C‐V characteristic, which explains the relation between the incident and reflected waves. This paper reports a simple experimental method of extracting reflected waves at a varactor load and presents estimates of the dynamic C‐V characteristic of the load. It is shown that the reflected voltage waves simulated using the dynamic C‐V characteristic agree with the measured results. © 2009 Wiley Periodicals, Inc. Electr Eng Jpn, 167(4): 32–38, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20821     

A 60‐GHz power amplifier design with on‐chip tunable load‐matching network and power detect in 90‐nm CMOS

This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

A three‐phase voltage‐source PWM inverter system characterized by sinusoidal output voltage with neither common‐mode voltage nor normal‐mode voltage

This paper deals with an inverter system integrating a small‐rated passive EMI filter with a three‐phase voltage‐source PWM inverter. The purpose of the EMI filter is to eliminate both common‐mode and normal‐mode voltages from the output voltage of the inverter. The motivation of this research is based on the well‐known fact that the higher the carrier or switching frequency, the smaller and the more effective the EMI filter. An experimental system consisting of a 5‐kVA inverter, a 3.7‐kW induction motor, and a specially designed passive EMI filter was constructed to verify the viability and effectiveness of the EMI filter. As a result, it is shown experimentally that both three‐phase line‐to‐line and line‐to‐neutral output voltages look purely sinusoidal as if the inverter system were an ideal variable‐voltage, variable‐frequency power supply when viewed from the motor terminals. This results in complete solution of serious issues related to common‐mode and normal‐mode voltages produced by the inverter. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(4): 88–96, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10206     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.     

Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.     

A novel active‐clamp zero‐voltage‐switching buck‐boost converter

An active‐clamp zero‐voltage‐switching (ZVS) buck‐boost converter is proposed in this paper to improve the performance of converter in light load condition. By employing a small resonant inductor, the ZVS range of switches could be adjusted to very light load condition. Moreover, 2 clamping capacitors are added in the converter to eliminate the voltage spike on the switches during transition. The operating principle of the proposed converter is analyzed, and the optimal design guide for full range ZVS is also provided. A 60‐W output prototype is experimentally built and tested in laboratory to verify the feasibility of proposed converter. The measured results show the critical ZVS operation of power switches at 1 and 0.7‐W output power for buck and boost mode, respectively. The peak conversion efficiency is up to 92.3%.     

An active‐clamping zero‐voltage‐switching flyback converter with integrated transformer

This paper proposes an active‐clamping flyback converter using an integrated transformer. The proposed converter is composed of two active‐clamp flyback converters. The presented converter can balance the total load current between secondary sides of two transformers so that the rectifier diode conduction loss is reduced. Also, the main switch of one converter is the auxiliary switch for the other converter, so that only two switches are required and both can achieve zero‐voltage‐switching operation. The two transformers are integrated into one magnetic core; therefore, the volume and copper loss of transformer can be reduced. Detailed analysis and design of this integrated magnetic active‐clamping flyback converter are described. Experimental results are recorded for a prototype converter with an AC input voltage ranging from 85 to 135 V, an output voltage of 24 V and an output current of 5 A, operating at a switching frequency of 100 kHz. Copyright © 2014 John Wiley & Sons, Ltd.     

A phase synchronization control scheme for LCL‐T type high‐frequency current source in parallel connection

Considering the applications of high voltage gate driving system and contactless power transmission, a current‐based power distribution is adopted as a kind of replacement of voltage based high‐frequency Alternating Current (AC) power distribution system. In order to implement high‐frequency current source, an LCL‐T resonant inverter is examined with constant current characteristic and high conversion efficiency. First, the resonant topology is studied as a high‐frequency power source, including circuit principle, operational cycle analysis, and AC analysis. The effective control and high conversion efficiency are both achieved by LCL‐T resonant inverter. Second, the phase angle control scheme is explored to improve the synchronization performance in parallel system formed by multiple of LCL‐T resonant inverters. Lastly, a prototype of parallel system is evaluated by simulation and experiment results, both of which are constructed by two resonant inverters with rated peak current of 2 A, rated output frequency of 30 kHz, and rated output power of 100 W. The experimental results in accordance with simulation prove that the better phase synchronization of output currents is achieved by the phase angle control. Hence, the high‐frequency resonant topology and phase control scheme are a feasible realization of current source that can be used to feed current‐based high‐frequency power distribution system. Copyright © 2015 John Wiley & Sons, Ltd. Index Terms—high‐frequency AC (HFAC), power distribution system (PDS), LCL‐T resonant inverter, current source, phase angle control.     

Switched‐capacitor‐voltage‐multiplier boost DC–AC inverter with adaptive stages

A multistage switched‐capacitor‐voltage‐multiplier inverter (SCVMI) is proposed with a variable‐conversion‐ratio phase generator and a sinusoidal pulse‐width‐modulation controller for boost DC–AC conversion and high‐efficiency regulation. Its power unit contains: SCVM booster and H‐bridge. The SCVM booster includes two m_c‐stage switched‐capacitor cells and two n_c‐stage switched‐capacitor cells in the interleaving operation to realize DC–DC boost gain of m_c × n_c at most. Here, the variable‐conversion‐ratio phase generator is suggested and adopted to change the running stage number and topological path for a suitable gain level of m × n (m = 1, 2, ?,m_c, n = 1, 2, ?,n_c) to improve efficiency, especially for the lower AC output. The H‐bridge is employed for DC–AC conversion, where four switches are controlled by sinusoidal pulse‐width‐modulation not only for full‐wave output but also for output regulation as well as robustness to source/loading variation. Some theoretical analysis and design include: SCVMI model, steady‐state/dynamic analysis, conversion ratio, power efficiency, stability, capacitance selection, output filter, and control design. Finally, the closed‐loop SCVMI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of this scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

A power‐efficient 600‐mVpp voltage‐mode driver with independently matched pull‐up and pull‐down impedances

In this study, a large‐swing, low‐power voltage‐mode driver with independently matched pull‐up and pull‐down impedances is proposed. To achieve large swing and constant impedances during a transition, a P‐over‐N structure is implemented with regulators calibrating the impedances. Two regulators are dedicated to matching the pull‐up and pull‐down impedances by regulating the supply voltages of the driver and predriver, respectively. Because background impedance calibration loops are adopted to track the process, voltage, and temperature (PVT) variations, the proposed driver can operate properly without additional calibration time. To reduce the power consumption of the calibration loops, scaled replicas of the actual driver are used. Moreover, an analysis of design optimization for the proposed driver is presented. The proposed driver was fabricated in 65‐nm CMOS technology and verified at a 5‐Gb/s data rate. Measurement results show that the proposed driver has a voltage swing of 600 mV_pp and a horizontal eye opening of 0.5 UI. The prototype chip consumes 6 mW at a 1.0‐V supply. Copyright © 2014 John Wiley & Sons, Ltd.     

An extensible two‐phase high voltage‐boosting converter with automatic current balance

In this study, an extensible 2‐phase interleaved high step‐up converter with automatic current balance is presented. This converter uses coupled inductors and energy‐transferring capacitors to improve the voltage gain of the traditional 2‐phase interleaved boost converter as well as employs these energy transferring capacitors to do automatic current balance. Furthermore, the voltage gain can be enhanced not only by adjusting the turns ratio but also by increasing the numbers of phases, diodes, and energy‐transferring capacitors. Therefore, it can be used in high input current and high step‐up voltage applications. In this paper, the basic operating principles of the proposed converter are described and analyzed, and finally, its effectiveness is demonstrated by experiment. In addition, the field‐programmable gate array, named EP13T100C8N and manufactured by Altera Co, is used as a control kernel, and an experimental prototype, with input voltage of 12 V, output voltage of 200 V, and rated output power of 200 W, is given to provide the effectiveness of the proposed converter.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel multi‐output high‐voltage‐isolated power supply system for semiconductor device series‐connected switches

This paper presents a novel scheme of a multi‐output power supply for solid‐state switches based on series‐connected semiconductor devices. By using the loosely transforming method, the system can realize high‐voltage isolation and a compact size, and its application range can be easily expanded to modular designed switch stacks for higher power ratings. The circuit structure and working principles are described. Based on the system operating equations, the design methodology is proposed and applied for parameter specification of a power supply system of two series‐connected switch stacks containing 20 outputs. Detailed calculations are given, and experimental results prove the feasibility of the proposed scheme. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

The effect of mismatch in current‐ versus voltage‐mode resistive grids

Resistive grids are commonly used in neuromorphic very large‐scale integration (VLSI) designs for image smoothing and signal aggregation. Because mismatch is inevitable in VLSI chips, one reason that resistive grids are attractive is that their output is robust to mismatch in the component values. Here, we examine relative sensitivity of different resistive grid designs that differ depending upon whether the input and output are represented by current or voltage. Our analysis reveals that a mixed‐mode design, where the input is represented by current but the output is represented by voltage, is less sensitive to mismatch when the amount of smoothing is large. On the other hand, when little smoothing is desired, pure voltage‐mode and current‐mode designs are preferred. From the point of view of mismatch sensitivity, there is little difference between the two pure‐mode designs. Our analysis also reveals that the difference in mismatch sensitivity is due to the vertical resistors, which are the most sensitive to mismatch in all the three designs studied. Copyright © 2008 John Wiley & Sons, Ltd.