基于FPGA的飞行校验多模信号采集与处理设计

针对仪表着陆系统(ILS)、甚高频全向信标(VOR)等的飞行校验需求,设计了一种基于FPGA的多模信号采集与处理系统。选用普通导航接收机接收信号,以FPGA作为逻辑和时序控制核心。系统包含了模拟信号调理和A/D转换、无线电系统总线(RSB)接口、ARINC 429总线接口、USB总线接口等的相应软硬件设计,首次在国内提出RSB软硬件实现方案。根据ILS与VOR的信号特点,并且分析了FPGA有限字长的影响,设计了数字滤波器,实现了在FPGA上的校验信号处理。经过验证,设计能够为飞行校验平台提供有效的数据,并且具备较强的可移植性,符合要求。     

基于FPGA的高精度多路温度采集器

描述了一个高精度多通道温度采集器的硬件设计和实现过程,系统采用AD590作为温度传感器、辅之以高质量数据放大器,可实现高精度温度测量;模数转换部分采用ADC0809;采集控制单元采用ALTERA的FPGA芯片实现。系统具有简洁可靠、开发周期短等特点。     

一个用于智能水电厂IED的GOOSE通信实现设计

IEC61850标准在智能水电厂的应用可以提高通信效率、实现数据共享。分析了智能变电站和智能水电厂中GOOSE应用的差异。提出了一种基于FPGA的智能水电厂IED的GOOSE通信实现设计。详细介绍了整体构架和报文收发软件设计。针对智能水电厂中交互信息类型多、数据量大等特点,设计了GOOSE报文硬件解码模块。利用FPGA的并行运算机制,在接收报文的同时完成解码与校验,进一步提升通信效率。仿真结果表明,该硬件解码模块满足智能水电厂GOOSE通信时效性和可靠性的要求。     

基于并行数据处理结构的电能质量在线监测

提出了基于现场可编程门阵列器件FPGA与数字信号处理器DSP并行结构的在线电能质量监测与分析。由FPGA同步产生系统控制时序,并充分利用FPGA与DSP各自在数字信号处理领域中的特点,在FP GA内设计了16位浮点FFT运算模块用于谐波分析,应用DSP实现电压波动与闪变等电能质量指标数据的计算,采用FPGA与DSP并行数据处理的方式,达到采样与数据处理的同步进行的目的,从而完成对多路信号的无缝采样与分析。     

HDB3编译码及其在Cyclone II FPGA的实现研究

为提高电缆测井数据传输的性能,提出一种基于HDB3码并利用Cyclone II系列FPGA的编、译码系统设计方案。详细分析了编译码的原理与实现方法,并在编译码实现过程中采用双相码来表示相应的码元,可以快速便捷地识别取代码,同时也解决了FPGA只能处理单极性电平的问题。在译码时特意先提取极性信息,故只需用一组移位寄存器来存放输入码流。最后给出了对应的仿真结果,并成功应用于石油测井领域的电缆测井数据通信系统研究装置中。     

人工神经网络FPGA硬件实现的研究进展

首先概述了人工神经网络FPGA硬件实现的发展状况,随后分析了FPGA实现神经网络的优势以及实现的关键技术,并探讨了实现过程中需要考虑的关键问题,最后指出了基于FPGA实现神经网络的研究方向。     

HDLC码流高精度时钟恢复电路的FPGA实现

提出了一种针对HDLC码流的高精度的时钟恢复电路。方案通过FPGA的可编程模块化设计,包含了小数分频、数据边沿采样、硬件倍频PLL及HDLC标志码脉宽测量等关键技术,实现从HDLC数据码流中恢复高精度时钟。经硬件实验验证,性能指标优秀,有较强的实用性,应用广泛。     

LDPC 码的多路并行编码器实现

针对空间数据系统咨询委员会(CCSDS)标准下低密度奇偶校验(LDPC)码编码器低硬件实现复杂度的应用需求,提出一种适用于不同码长、码率LDPC码的多路并行编码器实现架构。该架构通过重复利用编码器中的存储单元,将矩阵信息共享到所有并行的运算单元中从而提高资源利用率。进一步,在现场可编程门阵列(FPGA)平台上验证并测试码率分别为1/2、2/3及4/5的单路和多路编码器,测试结果表明采用多路并行架构的编码器吞吐量比单路编码器有明显的提高且均达到1 Gbps以上;与达到基本相同吞吐量的单路多组编码器相比,其查找表资源分别减少40%、44%和46%。该架构充分利用FPGA的存储资源进而有效降低硬件实现复杂度。     

基于FPGA的频谱分析系统研究与实现

针对音频信号分析,提出了一种基于 FPGA 的频谱分析系统,该设计基于 FFT 和 CORDIC 算法;讨论在FPGA上进行高达4096点的定点 FFT 运算和基于CORDIC算法的复数求模运算的系统架构和实现过程。通过Modelsim仿真,同MATLAB运算结果比较,本频谱计算方案的相对误差均值为4．11％。利用MCU进行信号采样与AD转换,并通过SPI接口将数据发送给FPGA进行频谱分析。当采样频率为60 kHz时,本系统辨识的频率范围为14．65 Hz～30 kHz ,频率分辨率为14．65 Hz。对实际硬件系统进行频谱分析测试,成功实现对输入的音频信号的频谱计算。     

基于TM S320C6713的图像采集处理系统设计

提出了一种采用DSP、FPGA及千兆以太网的混合结构的图像采集处理系统,以FPGA作为图像采集与相机控制模块,以浮点数字信号处理器TMS320C6713为图像处理核心,以千兆以太网为传输手段,从而在硬件上解决了图像数据的采集、处理与传输的问题。该文具体阐述了系统硬件总体结构及各个模块的功能与实现方法,并讨论了嵌入式软件的结构与处理流程。     

Prototype hardware realization of the DSTATCOM for reactive power compensation

This paper presents the hardware prototype implementation of a hysteresis current controller (HCC) based DSTATCOM for reactive power compensation. To compensate the desired amount of reactive power, the amount of current to be injected is calculated using the instantaneous reactive power theory. The reactive component of load current is set as the reference current. The VSC is operated in the closed-loop to supply the reference current. If the VSC supplies this reference current, the DSTATCOM is said to supply the required reactive power when connected to the grid. The performance of the DSTATCOM for reactive power compensation is studied in the prototype hardware using the field programmable gate array (FPGA) controller. The issues associated with the implementation of hardware prototype are discussed and the experimental setup is found to compensate the reactive power. The Spartan-3A DSP FPGA controller is programmed using the system generator feature in the MATLAB.     

民用飞机单粒子翻转问题研究

单粒子翻转(Single Event Upset,SEU)效应是机载复杂电子硬件设计所必须考虑的重要问题,对SEU效应进行了描述,分析了复杂电子设备经常用到的芯片类型(专用集成电路器件、反熔丝FPGA、SRAM型FPGA、Flash型FPGA)及其优缺点,总结了三模冗余、纠错码、擦洗、系统监控这四种常见的SEU减缓技术,对于国内民机机载复杂电子硬件的设计具有参考意义。     

行波故障定位系统中数据采集卡的设计与实现

提出一种用于行波故障定位系统的高速、高精度、多通道同步数据采集卡的设计和实现方法。首先给出了采集卡的总体结构及工作原理,然后详细介绍了采集卡硬件和软件的设计和实现思路。硬件以现场可编程门阵列(field programmable gate array,FPGA)为中央处理器,以高速、高精度、低功耗的模数转换器为信号转换单元,配备先进先出高速缓存,同步动态随机存储器和全球定位系统同步时钟接收模块。软件主要包括FPGA编程和外部设备互连PCI总线驱动程序。该采集卡能实现每路100 MHz的采样速率和16位高精度3路模拟输入的同步采集,并为采集的数据附加时标,可有效解决故障行波的高速、高精度数据采集问题。     

Real-time removal of impulse noise from MR images for radiosurgery applications

In the recent years, image processing techniques are used as a tool to improve detection and diagnostic capabilities in the medical applications. Among these techniques, medical image enhancement algorithms play an essential role in the removal of the noise, which can be produced by medical instruments and during image transfer. Impulse noise is a major type of noise, which is produced by medical imaging systems, such as MRI, computed tomography (CT), and angiography instruments. An embeddable hardware module, which can denoise medical images before and during surgical operations, could be very helpful. In this paper, an accurate algorithm is proposed for real-time removal of impulse noise in medical images. Our algorithm categorizes all image blocks into three types of edge, smooth, and disordered areas. A different reconstruction method is applied to each category of blocks for noise removal. The proposed method is tested on MR images. Simulation results show acceptable denoising accuracy for various levels of noise. Also, an field programmable gate array (FPGA) implementation of our denoising algorithm shows acceptable hardware resource utilization. Hence, the algorithm is suitable for embedding in medical hardware instruments such as radiosurgery devices.     

基于PC104＋双通道数据采集系统设计

PC104＋总线具有较多的优点,在嵌人式领域得到了越来越广泛的应用,研发基于PC104＋总线的通用双通道高速数据采集系统具有较强的实用价值。为了实现此采集系统,在硬件系统上,采用了PCI9054接口芯片、大容量的FPGA和双口RAM、两片AD6640作双通道数据采集的结构。在软件系统上,采用了底层驱动程序、开发函数库、上层应用软件的结构。经实际测试,该系统能稳定工作,完成双通道数据采集。因此,本文提出的数据采集系统硬软件结构及实现方法具有实用及参考意义。     

Multidimensional binary search calculation of the neuron model

Artificial neural networks have the potential for parallel processing with integrated circuit technology. Over 1 million gates are now available in the latest FPGA (Field Programmable Gate Array). However, the sum‐of‐product circuit used for evaluating inputs of the neuron model is complex and not effective for hardware implementation by FPGAs. In this paper, an improved calculation algorithm of the perceptron‐type neuron model is proposed, based on multidimensional binary search. Since the search does not need the sum‐of‐product circuit, the designed neuron circuit is small and fast. It is suitable for hardware implementation. © 2001 Scripta Technica, Electr Eng Jpn, 138(2): 24–32, 2002     

Adaptive Boolean Logic Using Ferroelectrics Capacitors as Basic Units of Artificial Neurons and Its Implementation in FPGA

In this work we propose the implementation of boolean logic through artificial neurons with Ferroelectric Capacitor (FeCapacitor) as its basic unit on a reconfigurable hardware platform. Two neurons were implemented: the Perceptron and the Spiking Neuron model. Both neurons use the phenomenon of the hysteresis loop as an activation function and were embedded on a Field Gate Programmable Gate Array (FPGA) hardware platform. The implementations were carried out by Simulink models and hardware synthesizable blocks from DSP Builder software and the results are shown in the form of the models and the boolean functions implemented by them.     

基于FPGA的多传感数据融合电子式互感器采集系统仿真

提出了一种基于FPGA和AD7685的电子式互感器采集系统的设计方案,给出了具体的基于多传感数据融合技术的积分方法,在FPGA中采用Verilog HDL语言编程控制AD7685进行数据采样,并将采样数据加上CRC校验码后按规定的帧格式组帧,最后通过串口按曼彻斯特码发送.由于电子式互感器的采集系统处于高压侧,受到激光电...     

A reconfigurable real-time neuromorphic hardware for spiking winner-take-all network

The central nervous system receives a vast amount of sensory inputs, and it should be able to discriminate and recognize different kinds of multisensory information. Winner-take-all (WTA) consists of a simple recurrent neural network carrying out discrimination of input signals through competition. This paper presents a real-time scalable digital hardware implementation of the spiking WTA network. The need for concurrent computing, real-time performance, proper accuracy, and the reconfigurable device has led to the field-programmable gate array (FPGA) as the target hardware platform. A set of techniques is employed to lessen memory and resource usage. The proposed architecture consists of multiprocessing elements, which share hardware resources between a specific number of neurons. We introduce a novel connectivity array for neurons (dedicated to the WTA network) to cut down memory usage. Also, a multiplier-less method in the neuron model and a novel tree adder in the synapse processing unit are designed to improve computational efficiency. The proposed network simulates 4,500 neurons in real time on a Xilinx Artix-7 FPGA, while a scalable architecture facilitates the implementation of up to 20,000 neurons on this device. The pipeline structure can guarantee real-time performance for large-scale networks. Based on simulation and physical synthesis results, the presented network mimics biological WTA dynamics and consumes efficient hardware resources.