Frequency–amplitude relations for cross‐coupled voltage‐controlled oscillator

Dependence of frequency on amplitude and control bias is considered for the cross‐coupled voltage‐controlled oscillator. Closed form expressions are derived for frequency of oscillation as a function of amplitude, for positive and negative control bias voltages. Theory of nonlinear ordinary differential equations is utilized to show that the capacitance–voltage relation is the main cause of frequency shift with amplitude. Furthermore, the case of small amplitudes relative to control voltage is analyzed, and a closed form expression is derived for dependence of frequency on amplitude. This relation is then verified using the concept of effective capacitance. The effective capacitance approach is also used to extend the analysis to large voltage swings. Dependence of frequency on tuner control voltage is calculated for both bias polarities. Implications of the aforementioned equations for voltage‐controlled oscillator performance are discussed. Numerical calculations and simulations are used to compare and verify the closed form equations, showing good agreement. Copyright © 2012 John Wiley & Sons, Ltd.     

A three‐phase voltage‐source PWM inverter system characterized by sinusoidal output voltage with neither common‐mode voltage nor normal‐mode voltage

This paper deals with an inverter system integrating a small‐rated passive EMI filter with a three‐phase voltage‐source PWM inverter. The purpose of the EMI filter is to eliminate both common‐mode and normal‐mode voltages from the output voltage of the inverter. The motivation of this research is based on the well‐known fact that the higher the carrier or switching frequency, the smaller and the more effective the EMI filter. An experimental system consisting of a 5‐kVA inverter, a 3.7‐kW induction motor, and a specially designed passive EMI filter was constructed to verify the viability and effectiveness of the EMI filter. As a result, it is shown experimentally that both three‐phase line‐to‐line and line‐to‐neutral output voltages look purely sinusoidal as if the inverter system were an ideal variable‐voltage, variable‐frequency power supply when viewed from the motor terminals. This results in complete solution of serious issues related to common‐mode and normal‐mode voltages produced by the inverter. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(4): 88–96, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10206     

Analysis and design of voltage‐controlled current sources for a grounded load

The paper presents the structure and the principle of operation of the ‘improved’ Howland current pumps (or voltage‐controlled current sources (VCCSs) for a grounded load). In particular, under review is the VCCS employing power operational amplifier (op amp) and the VCCS using low power op amp and an additional power transistor, extending working dynamic range. On the basis of analysis of the operational principle, the equations for transfer functions of both circuits and formulas for the related dynamic electrical parameters are obtained. Moreover, using these formulas, a design procedure is developed, and recommendations for simulation modelling are given. The efficiency of the proposed procedure is verified by simulation modelling and experimental testing of sample electronic circuits of VCCSs. Copyright © 2013 John Wiley & Sons, Ltd.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.     

A novel multi‐output high‐voltage‐isolated power supply system for semiconductor device series‐connected switches

This paper presents a novel scheme of a multi‐output power supply for solid‐state switches based on series‐connected semiconductor devices. By using the loosely transforming method, the system can realize high‐voltage isolation and a compact size, and its application range can be easily expanded to modular designed switch stacks for higher power ratings. The circuit structure and working principles are described. Based on the system operating equations, the design methodology is proposed and applied for parameter specification of a power supply system of two series‐connected switch stacks containing 20 outputs. Detailed calculations are given, and experimental results prove the feasibility of the proposed scheme. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

A configuration for realizing floating,linear, voltage‐controlled resistance,inductance and FDNC elements

A configuration using current feedback amplifiers has been presented, which is capable of realizing linear, positive/negative voltage‐controlled resistance, voltage‐controlled inductance and voltage‐controlled frequency‐dependent negative conductance in floating form (and thereby, also in grounded form) from the same structure. The workability of the proposed configuration has been demonstrated by hardware implementation results using AD 844‐type current feedback op‐amps (CFOAs) and BFW‐11‐type JFETs and the workability in high‐frequency range has been demonstrated by SPICE simulation using CMOS CFOAs. Copyright © 2008 John Wiley & Sons, Ltd.     

A CCII‐based non‐inverting Schmitt trigger and its application as astable multivibrator for capacitive sensor interfacing

This paper presents a novel second‐generation current conveyor (CCII)‐based non‐inverting Schmitt trigger topology. By means of the use of only three resistances, it is possible to set easily the threshold values or, in addition, the trigger can be set also to work as a zero‐voltage comparator. The theoretical working principle has been confirmed through PSpice simulations implementing an integrated CCII, designed in a low‐cost standard complementary metal–oxide–semiconductor technology (Austria Micro Systems (AMS) 0.35 µm) with low‐voltage low‐power characteristics, and then by experimental tests on the fabricated printed circuit board prototype through the use of the commercial component AD844 (Analog Devices) as CCII. As its main application example, the presented trigger has been employed to implement an astable multivibrator proposed here as a capacitive sensor interface capable to accurately detect about five decades of capacitive variations in the range of [100 pF–5.5 μF] with a maximum relative error lower than ±10%. Copyright © 2016 John Wiley & Sons, Ltd.