A programmable analog baseband filter with DC offset reduction using servo loop feedback

This paper presents a programmable analog baseband filter with direct current (DC) offset cancelling, using the standard complementary metal‐oxide‐semiconductor process. The servo loop feedback topology is adopted to reject in‐band DC offset at each stage of the receiving system. Furthermore, the proposed back‐to‐back diode‐connected configuration forms an ultrahigh pseudo resistor, which is applied in the feedback path of the integrator to obtain an ultralow cut‐off frequency (<1 Hz) for the high‐pass response. Therefore, low‐frequency application is possible for simultaneously in‐band DC offset and out‐band interference suppression. A servo loop feedback system with a pseudo resistor is used in the analog baseband filter to verify the concept. The chip is fabricated by using the TSMC 0.13‐um complementary metal‐oxide‐semiconductor process and consumes 43.8 mA from a 1.2 V DC supply voltage. The measured gain variation is from 65.6 to ?3.3 dB with a resolution of 1 dB at a bandwidth of 5 MHz. The bandwidth is adjustable from 1.75 to 10 MHz.     

Realizations of fully differential voltage second generation current conveyor with an application

Three novel CMOS realizations for the fully differential voltage second‐generation inverting current conveyor (FDVCCII‐) are proposed in this paper. The first realization has a limited input range, and the other two realizations have a rail to rail input range and show excellent features in linearity and bandwidth. As an application to the FDVCCII‐, a floating gyrator is proposed. A floating inductor is realized using the floating gyrator and it is used in realizing a second‐order low‐pass filter, which is simulated and compared with the ideal result. All circuits are simulated with SPICE using CMOS 0.35µm technology and supply voltages ±1.5V to verify the theoretical results. Copyright © 2008 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

A class of digitally programmable nth‐order filters

A family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.     

CMOS digitally programmable quadrature oscillators

CMOS digitally programmable quadrature oscillators based on digitally controlled current followers and voltage followers are proposed. The proposed designs provide the advantage of programmability similar to the operational transconductance amplifier‐based oscillators while offering improved linearity. In mixed analog/digital systems, the digital tuning feature allows direct interfacing with the digital signal processing part. Novel realizations that provide both voltage‐mode and current‐mode quadrature sinusoidal signals are presented. Employing only grounded capacitors the designs achieve independent control of the frequency and condition of oscillation that can be tuned digitally. Experimental results obtained from a 0.35 µm CMOS chip fabricated using standard CMOS process are given. Copyright © 2008 John Wiley & Sons, Ltd.     

First direct implementation of a true random source on programmable hardware

True random sources are not implementable in digital hardware, so that many practical applications have historically relied on pseudo‐random generators in order to avoid the potentially long prototyping times and the costs of dedicated analog design. However, pseudo‐random sources have liabilities that make them hardly suitable for some tasks (notably security related ones). Previous attempts to conciliate security, cost‐effectiveness, and rapid development included the exploitation of the analog accessory parts often present on programmable devices. In these designs some analog blocks are used for their side effects (noise amplification) rather than for their originally intended behaviour. Conversely, here we report a direct implementation of a true random source on programmable, low‐cost, general‐purpose hardware, where all blocks are used only for their nominal function. To the best of the authors' knowledge, this is the first proposal of this sort. The design exploits an FPAA, and is based on a non‐linear system exhibiting chaotic behaviour. Measures confirm the correct operation, high throughput, and robustness of the system. Copyright © 2005 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A high‐order curvature‐corrected CMOS bandgap voltage reference with constant current technique

A high‐order curvature‐corrected complementary metal–oxide–semiconductor (CMOS) bandgap voltage reference (BGR), utilizing the temperature‐dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35‐µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 μW at room temperature (25 °C), and the temperature coefficient of the output voltage reference is about 5.5 ppm/°C from −40 °C to 125 °C. The measured power supply rejection ratio is −38.8 dB at 1 kHz. The BGR is compatible with low‐voltage and low‐power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.     

Current‐mode wave field programmable analogue arrays

A new configurable analogue block (CAB), the key element in the design of field programmable analogue arrays (FPAAs), is introduced in this paper. This CAB is based on wave equivalents of the passive elements and it is easily reconfigurable resulting in very simple and versatile FPAA structures. The proposed topology employs a minimum number of switches in the signal path due to the absence of the interconnection network required in other FPAA structures, and thus an improved performance is achieved in comparison with the already introduced corresponding programmable configurations. Copyright © 2008 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

Using MOS current dividers for linearization of programmable gain amplifiers

Two highly linear, digitally programmable gain amplifiers are presented and compared in terms of linearity, frequency, area and power consumption. High linearity and wide gain tuning range with moderate area consumption are the main benefits of both configurations. Furthermore, constant bandwidth is achieved by means of switched compensation capacitor arrays. Three‐bit prototypes were integrated in a 0.35 µm–3.3 V CMOS process with 2.5 V supply voltage. Experimental distortion levels are better than ?68 dB for 1 MHz and 1 V_p?p output signals in both configurations; hence, the suitability of the linearization technique based on MOS current dividers is shown. Copyright © 2007 John Wiley & Sons, Ltd.     

特种开关电源关键电路的设计方案

特种开关电源是指为满足用户特殊需要而开发的产品。首先介绍恒压／恒流控制环的基本原理和设计方法,然后阐述利用可编程精密基准电压源和辅助电源设计从ov起调的隔离式开关电源的解决方案,最后介绍多个开关电源模块并联使用的要点,并给出一种并联供电系统的设计方案。     

High‐voltage compliant microelectrode array drivers for intracortical microstimulation

We present in this paper two low‐power high‐impedance microelectrode array drivers (MEDs) dedicated for visual intracortical microstimulation. These output stages of a new microstimulator are highly configurable and able to deliver higher compliance voltage (20 V for anodic and cathodic phases) across microelectrode‐tissue interface impedance compared with previously reported designs. Each MED is featured with a high‐voltage switch‐matrix, 3.3 V/20 V current mirrors, an on‐chip 32‐bit serial‐in parallel‐out shift register, and the new forbidden state logic circuits. Both systems are able to deliver eight bipolar or 16 monopolar stimulation simultaneously. The first MED is able to deliver one stimulation current level and the second one provides four different current amplitudes simultaneously to 16 electrodes. Two microchips have been designed and fabricated using Teledyne DALSA 0.8 µm 5V/ 20v double‐diffused metal‐oxide‐semiconductor field‐effect transistor (Teledyne DALSA Semiconductor, Bromont, Québec, Canada) technology to meet the required high‐voltage compliance. The nominal values of largest supply voltages are ±10 V. The maximum stimulation current per input channel is 400 μA and per output channel through an emulated microelectrode impedance of 100 kΩ is 100 μA. The measured output compliance voltage is 10 V/phase (anodic or cathodic) for the specified supply voltages. Increment of supply voltages to ±13 V allows 220 μA stimulation current per output channel enhancing the output compliance voltage up to 20 V/phase. The measured quiescent power consumptions of the proposed microelectrode array drivers are 316 and 735 μW, respectively. Post‐layout simulation and measurement results of two MEDs and comparison with other designs have been reported in this paper. Copyright © 2015 John Wiley & Sons, Ltd.     

A complementary metal–oxide semiconductor digitally programmable current conveyor

A second‐generation current conveyor with digitally programmable current gains is presented. A current division network with zero standby power consumption is utilized in two different ways to provide both gain and attenuation of the second‐generation current conveyor's current transfer characteristics. The proposed topology overcomes several drawbacks of the previous solutions through affording a more power and area efficient solution while exhibiting relatively wider tuning range and bandwidth. A variable‐gain amplifier and a two‐integrator‐loop filter biquad providing low‐pass and band‐pass responses are given as application examples. A modified two‐integrator‐loop topology is developed to offer independent control of the pole frequency and quality factor without disturbing the passband gain. Simulation results obtained from a standard 0.18 µm complementary metal–oxide semiconductor process are given. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

基于DSP控制的低压大电流开关电源设计

设计了一款DSP控制的全数字化低压大电流开关电源。详细分析了主电路、恒压恒流控制策略和死区时间设定等电路,并针对桥式变换器桥臂直通问题,提出了一种抗干扰的驱动电路设计。最后在实验室制作的3k W(15V/200A)电源验证了电路设计的可行性,给出了详细的实验波形和数据,对开关电源设计工程师有一定的借鉴作用。     

Analysis and design of a high‐compliance ultra‐high output resistance current mirror employing positive shunt feedback

This paper reports a novel high‐compliance, very accurate and ultra‐high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra‐high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post‐layout simulations. Designed in the IBM 130‐nm standard CMOS process, the circuit consumes 230 × 110 µm² of silicon area. Post‐layout simulation results indicate that with a 3.3‐V power supply, output voltage compliance of 0.93V_Supply is achieved at a maximum output current of 96 μA. Moreover, an extremely ultra‐high output resistance of 320 GΩ is achieved, which is one of the highest reported values of output resistance for current mirrors implemented using regular CMOS technology. The ?3 dB upper cut‐off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 μA to the load. Copyright © 2014 John Wiley & Sons, Ltd.     

The CCII+ and the ICCII as basic building blocks in low‐pass filter realizations

Three new grounded capacitor current mode low‐pass filters using two inverting second‐generation current conveyor (ICCII) or one double output ICCII are given. The circuits employ the minimum number of passive circuit components, namely two resistors and two capacitors. The circuits are generated from three new voltage mode low‐pass filters realized with the ICCII. A new grounded capacitor CCII+ current mode low‐pass filter is generated from one of the new voltage mode low‐pass filters employing two ICCII?. A new grounded passive component low‐pass filter with independent control on Q and using three ICCII+ is also introduced. Spice simulation results based on using the 0.5 µm CMOS model are included to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.