基于相分量模型考虑零序互感线路的跨线故障计算方法

基于输电线路的相分量模型,提出了利用相分量法对同杆并架线路上的跨线故障进行计算的方法。根据跨线接地故障与跨线不接地故障的通用接口情形推导出其相分量节点导纳矩阵统一模型,在此基础上提出了同杆并架线路上发生典型跨线故障时的节点导纳矩阵模型及其算法。通过典型跨线故障算例表明了该模型及算法适合于编制通用的跨线故障计算程序。仿真结果证实了该模型及算法的正确性。     

ACTIVE LINEAR DC CIRCUIT MODELS FOR POWER SYSTEM ANALYSIS

Abstract

The nonlinear equations encountered in steady state and transient analysis of power systems are often linearized for use in iterative methods or small change sensitivity studies such as dynamic stability. In this work, the standard constant power constraints are linearized and represented as active linear DC electronic circuits. The model is an exact small signal representation and maintains the fundamental voltage/current variables in the original nonlinear circuit model. The circuits can be reduced using standard Norton/Thevenin equivalent techniques.     

微信号检测的调理电路研究

本文通过对光纤位移传感器的调理电路研究 ,总结出降低微信号检测系统调理电路噪声的分析方法和实施措施。对微弱光信号的相位调制和电路、数字解理过程 ,给出了低噪声设计的理论依据、电路参数的选取原则和前置放大器设计的一般方法。所研制的调理电路与传感器相配合 ,使微小位移的分辨力达 0 0 0 5nm     

Positive‐real property of passive fractional circuits in W‐domain

Fractional circuits have attracted extensive attention of scholars and researchers for their superior performance and potential applications. Fractional circuits constitute a new challenge for the analysis and synthesis methods of traditional circuits theory. Passivity is the fundamental property of traditional circuits (integer order electric circuits). As is known to all, passivity is equivalent to positive realness in traditional linear circuits. However, this equivalence is broken down by introducing fractional elements into electrical networks in s‐domain. To address this issue, on the basis of s‐W transformation, we study the passive criteria of fractional circuits with rational order elements in this paper. Definitions of positive‐real (matrix) function in W‐domain are given, and the equivalence conditions of positive realness are derived. In addition, a conclusion is proposed in which the immittance (matrix) function of passive fractional circuits with rational order elements is positive real in W‐domain. The applications of passive criteria in circuit synthesis are shown.     

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Multi‐voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire‐bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi‐voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time‐consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency. Copyright © 2015 John Wiley & Sons, Ltd.     

电力系统谐波的一种新的单相检测法

在瞬时无功功率理论的基础上,针对一般基于d-q变换的检测方法不能检测不对称三相电流的谐波的缺点,提出了一种新的电网谐波检测方法。此方法属于单相检测法,先提取电网电流中的某相基波幅值,再将基波幅值乘以与该相电流同相位的正弦波,从而得出该相的瞬时基波电流。该方法相对简化了结构,并且采用了改进的算法,能很好地运用于单相电路和三相电路的谐波检测。仿真结果表明,在电网三相电流对称和不对称的两种情况下,这种方法都能保证检测的实时性和精确性。     

同相牵引供电系统中无锁相环的电流检测方法研究

为了实时准确的补偿同相铁路负载侧的基波无功电流与谐波电流,使三相电源侧的功率因数为1,从而达到三相平衡。传统的方法是利用三角函数正交特性,用加法器,乘法器,积分器,锁相环来实现基波有功电流与无功电流的检测。虽能避免大量的矩阵与反矩阵的运算,使整个电路成本变低,易于实现,但由于单相锁相环特有的相位延时,使得在锁定电压会产生初期的相位偏差,加上低通滤波器固有的延时,严重影响了电流检测的动态性能。基于上述问题,考虑到均值滤波器特有的快速响应性能,文章提出一种基于Scott平衡变压器同相牵引供电模型下的负载基波有功电流与基波无功电流的改良检测方法,用均值滤波器来替代传统的低通滤波器与单相锁相环来锁定被测电压的相位与频率,从而使检测的基波有功与无功电流更加的准确,理论分析与仿真验证了该方法的可行性与优越性。     

混合信号集成电路衬底噪声的一种连续时间直接测试方法

建立了混合信号集成电路中衬底噪声对模拟电路影响的一种通用模型，在此基础上，提出了衬底噪声测试的一种新的连续时间直接测试方法。该方法采用差分放大器作为衬底噪声探测器，能测试频率高达1GHz的衬底噪声。     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.     

同杆双回路不同换位下模量分析

提出一种求解不同换位方式下同杆双回路相模阻抗变换方法,并求出了3种常见换位方式下的阻抗矩阵和转换矩阵,转换矩阵中不含复数元素及阻抗矩阵完全对角化的特点,为新型同杆双回路故障定位和选相保护提供了理论基础。电磁暂态（EMTP）计算验证了该方法的正确性。     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

基于基波电势分布特征的大型发电机定子接地故障定位方法

提出一种基于基波电势分布特征的定子接地故障定位方法,该方法按各相各分支定子线圈的实际连接关系,确定发电机中性点至接地故障点的基波电势,建立了该基波电势、机端三相基波电压、基波零序电压、接地过渡电阻阻值之间的数学关系,准确定位定子接地故障,并对波绕组发电机故障定位中的特殊情况进行了分析。采用基于准分布电容参数的定子接地故障仿真模型验证了所提方法的有效性。最后对现场实际故障案例进行分析,进一步验证了所提方法的准确性,其可大幅缩短现场故障检修的时间。     

A simulation tool for the analysis and verification of the steady state of circuit designs

Analogue and microwave design requires accurate and reliable simulation tools and methods to meet the design specifications. System properties are often measured in the steady state. Well-suited algorithms for calculating the steady state can be classified into shooting methods, finite difference methods and the harmonic balance (HB) technique. Harmonic balance is a frequency domain method which approaches the problem of finding the steady state by a trigonometric polynomial. Depending on the size of the circuit and the number of Fourier coefficients of the polynomial, the resulting system of non-linear equations can become very large. These non-linear equations are solved by using Newton's method. The sparse linear system arising from Newton's method can be solved by direct, stationary or non-stationary iterative solvers. Iterative methods are normally easy to parallelize or vectorize. In this paper a tool for the simulation of the steady state of electronic circuits is presented. the steady state is calculated using the harmonic balance technique. Non-linear equations are solved by Newton's method and linear equations by preconditioned non-stationary iterative solvers (CGS, Bi-CGSTAB, BiCGSTAB(2), TFQMR). the run time is reduced dramatically, by up to an order of magnitude.     

锁相环相位噪声的研究与仿真

锁相环在数字电路中一个重要的应用就是作为频率合成器产生高性能的时钟。本文介绍了锁相环的工作原理,重点研究了锁相环输出时钟的相位噪声的影响因素。通过对其线性环路模型进行频域分析,运用反馈控制理论,讨论了环路内各器件的噪声对其输出信号相位噪声的影响。得到了锁相环能良好改善环路带内噪声的分析结果,并且利用ADS搭建仿真电路,验证分析结果,为今后高性能频率合成器的设计和应用提供参考依据。     

基于Hanning卷积窗的DFT介质损耗角测量算法

在高压电气设备介质损耗角在线监测中,DFT算法用于介质损耗角(介损角)测量时,系统频率的波动所造成的非同步采样将会产生泄露效应,从而会影响介损角测量精度。文章详细地分析了DFT算法非同步采样造成的泄露效应,提出了一种基于Hanning卷积窗的DFT介质损耗角测量算法。该算法采用Hanning卷积窗对电流和电压信号进行加权,利用频谱相位差校正法进行频谱校正以获得基波相位,根据电流与电压的基波相位差计算出介损角。通过仿真给出了该算法在电压频率波动和白噪声变化时计算所得介损角的变化情况,通过分析验证了该算法的有效性。     

基于Prony谱线估计方法的间谐波检测

传统的谐波分析方法都是基于傅立叶变换,认为只有谐波周期均为基波周期的整数倍。然而,实际存在的间谐波周期与基波周期不成整数倍关系,要正确检测出间谐波,必须以间谐波与基波周期的最小公倍数作为检测周期,因此,FFT算法无法在较短的时间内精确检测到信号中的谐波和间谐波成分。将Prony谱线估计方法应用到间谐波检测中,推导出间谐波频率、幅值和相位的计算公式。仿真验证了该算法要优于FFT算法,对间谐波和谐波的幅值、频率和相位的估计具有很高的精度。     

Discontinuity correction in piecewise‐linear models of oscillators for phase noise characterization

Decomposition of noise perturbation along Floquet eigenvectors has been extensively used in order to achieve a complete analysis of phase noise in oscillator. Piecewise‐linear approximation of nonlinear devices is usually adopted in numerical calculation based on multi‐step integration method for the determination of unperturbed oscillator solution. In this case, exact determination of the monodromy matrix can be hampered by the presence of discontinuities between models introduced by the approximation. In this paper we demonstrate that, without the proper corrections, relevant errors occur in the determination of eigenvalues and eigenvectors, if adjacent linear models presents discontinuities. We obtain this result by the analysis of a simple 2‐D oscillator with piecewise‐linear parameter. We also demonstrate that a correct calculation can be achieved introducing properly calculated state vector boundary conditions by the use of interface matrices. This correction takes into account the effects of discontinuities between the linear models, leading to exact calculation of eigenvalues and eigenvectors, and, consequently, of the phase noise spectrum. Copyright © 2006 John Wiley & Sons, Ltd.     

NHAR: A non‐homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports

Large‐scale RCL circuits with a large number of ports have been widely employed to model interconnect circuits, such as the power/ground networks, clock distribution networks and large data buses in VLSI. The input‐dependent moment‐matching technique, which takes the input excitations into account when constructing the projection matrices for the reduced‐order systems, has been proposed to simulate this type of circuits. The existing input‐dependent moment‐matching methods suffer from either numerical instability in the case of extended Krylov subspace (EKS) and improved extended Krylov subspace (IEKS) methods, or unbearable memory consumption and CPU cost for the EXPanded LINearization (EXPLIN) method. In this paper, a Non‐Homogeneous ARnoldi (NHAR) process, which consists of a memory‐saving and computation‐efficient linearization scheme and a numerical stable partial orthogonalization Arnoldi method, is proposed for the generation of the orthonormal projection matrix. By applying the obtained projection matrix to generate the reduced‐order model, we derive the NHAR method for the model‐order reduction of large‐scale RCL circuits with a large number of ports. The proposed NHAR method can guarantee moment matching, numerical stability and passivity preserving. Compared with the EXPLIN method, NHAR can remarkably reduce the size of the linearized system and therefore can greatly save the memory consumption and computational cost with almost the same accuracy. Moreover, NHAR is numerically stable and can achieve higher accuracy with approximately the same computational cost compared with the EKS and IEKS methods. Copyright © 2009 John Wiley & Sons, Ltd.     

Thermal noise analysis of switched‐capacitor integrators with correlated double sampling

Correlated double‐sampling (CDS) is widely used to suppress the effect of flicker noise in switched‐capacitor (SC) circuits. Once the flicker noise is suppressed by CDS, the noise of the SC circuits is ultimately determined by the thermal noise. In this work, we develop a method to calculate the thermal noise in SC integrators as functions of a variety of circuit parameters such as capacitor size and switch resistance; this methodology is then applied to a CDS integrator as well as a conventional integrator. We found that for the CDS integration scheme, in order to avoid significantly increasing the noise power of the integrator, the size of the CDS capacitor should be comparable to that of the sampling capacitor. We also found that if the CDS capacitor is sufficiently large, the noise power of a CDS integrator is almost the same as that of a conventional integrator with the same sampling capacitor size. These findings are explained based on the bandwidth of the transfer functions. Copyright © 2016 John Wiley & Sons, Ltd.     

On stochastic modelling of linear circuits

In this paper, the deterministic modelling of linear circuits is replaced by stochastic modelling by including variance in the parameters (resistance, inductance and capacitance). Our method is based on results from the theory of stochastic differential equations. This method is general in the following sense. Any electrical circuit that consists of resistances, inductances and capacitances can be modelled by ordinary differential equations, in which the parameters of the differential operators are the functions of circuit elements. The deterministic ordinary differential equation can be converted into a stochastic differential equation by adding noise to the input potential source and to the circuit elements. The noise added in the potential source is assumed to be a white noise and that added in the parameters is assumed to be a correlated process because these parameters change very slowly with time and hence must be modelled as a correlated process. In this paper, we model a series RLC circuit by using the proposed method. The stochastic differential equation that describes the concentration of charge in the capacitor of a series RLC circuit is solved. Numerical simulations in MATLAB are obtained using the Euler–Maruyama method. Copyright © 2008 John Wiley & Sons, Ltd.