一种新的处理器间光互连网络

随着计算机系统对互连网络性能需求的提高,传统的电互连技术出现了许多无法克服的问题,光互连技术应运而生。本文设计了一种新的基于高速光开关的处理器间光互连结构——PIBOS,并在此基础上提出了单级PIBOS和多级PIBOS中的链路仲裁和路由算法。模拟结果表明,采用PIBOS互连结构,减少了数据传输过程中的光电转换操作,提高了网络的吞吐率,降低了系统延时,并很好地实现了互连系统的扩展。     

PCI Express技术在嵌入式MPSoC中的应用

PCI Express作为第三代高性能I/O互连技术具有很多技术优势,如基于报文交换、点对点连接、LVDS高速串行互连、高带宽等。但是,PCI Express技术更多地应用于通用高性能计算机领域,鲜有将其应用于嵌入式系统设计中的实例。本文基于自行研制的一款嵌入式多核SoC系统YHFT-QDSP,根据系统设计需求,结合PCI Express技术特点,采用基于IP裁剪的快速设计方法将PCI Express技术应用于系统片间互连模块的设计中,缩短了设计周期并获得了良好的设计效果。采用0.13μm工艺单元库实现,PCI Express片间互连模块总面积为0.65mm2,其中协议转换模块面积为0.12mm2,片间数据传输有效带宽可达1.63Gb/s。     

基于正交调制的IP-over-WDM光标记交换网络

详细阐述了基于正交调制格式的IP-over-WDM光标记交换网络的网络体系结构,给出了边缘路由器的结构图与核心路由器的实现方法,最后给出了基于正交调制格式的IP-over-WDM光标记传输实验,实验中的标记信号速率为312 Mb/s,净荷速率10Gb/s,在标准单模光纤(SMF)上实现了88km传输,实验结果表明了所述方案的可行性.     

泰科电子推出用于光收发器的互连系统

<正> 近日,泰科电子推出兼容CFP的互连系统,为40 Gb/s和100 Gb/s以太网应用提供热插拔解决方案。这套兼容CFP的互连组件包括收发器模块插头连接器、连接于主板的主机插座连接器、附属导轨、插座上盖、外部托架组件、固定垫板组件和凹形散热片等。CFP MSA封装规格由光收发器领域的领先厂商创建,确立了热插拔光收发器的封装标准,推动了40 Gb/s和100 Gb/s应用的发展。热插拔兼容CFP的收发器将满足数据通信和电信级网络对超高带宽的要求,可应用于长距离回程到数据中心间的传输设备中,例如由器、交换机和光传输设备等。     

光互连技术的探讨

讨论了电互连方式的缺陷以及光互连方式的优点，介绍了当前光互连的基本情况。通过对一个具体光互连模型的分析，论述了光互连的基本原理及光学实现技术。最后叙述了光互连模型实现ｎ维超立方的算法。     

高性能光互连机群网络接口卡的设计与实现

由于网络环境的机群系统中单个结点的性能越来越高，机群互联网的通信带宽和可靠性成为提高系统性能的主要因素。该文提出了基于计算机DDR存储器接口的高性能光互连机群网络接口卡的结构，并在Xilinx公司的FPGA芯片XC2VP20上进行了实现，对高性能机群互连链路瓶颈问题的解决做了探索性的尝试。实际测试结果表明，DDR存储器接口带宽达到了1600MB／s，链路单通道的最高实测速率达到2．5Gb／s。     

基于硅光子的片上光互连技术研究

随着芯片半导体工艺的发展,芯片集成度不断提高,单个芯片上所能容纳的计算核心数越来越多,使得核心间的数据移动效率成为制约处理器芯片整体性能的关键因素。光互连技术采用波导方式传输数据,信号传输的损耗低、速度快、延迟小,它通过采用波分复用(WDM)技术可以达到很高的带宽密度,有助于解决片上通信的瓶颈问题。面向未来片上高性能互连的需求,深入分析了电互连技术的现状与局限性,研究并分析了基于硅光子的光互连技术发展现状和趋势,对比了多种典型光互连架构的特点及优缺点,总结了未来硅光子互连技术需要解决的5个重要问题。     

超高速光纤通信数据采集系统

以10Gb／s速率为例,介绍了超高速光纤通信信号接入系统的设计和实现。本文分别从总体设计、硬件实现及软件实现三个方面进行描述,并着重介绍了系统重点环节信号的接收和外接存储体设计,其中接收部分主要由光电转换模块与FPGA（Field programmable gatearray）完成,外接存储体主要由DDRSDRAM构成。最后给出了光数据采集系统的测试方法和实验结果,结果证明系统完全可以实现10Gb／s速率以下的光数据接入采集。     

400Gb/s热插拔光收发模块测试系统研究

通信网络从100 Gb/s向400 Gb/s演进,是近年来的研究热点.光收发模块是其中的核心部件之一.光模块的测试是开发和生产过程中必须要面对的问题.在400 Gb/s光模块中引入了调制格式为四阶脉冲幅度调制(PAM4)的光电信号,其参数定义和测试方法不同于传统的不归零码(NRZ)信号.按照400 Gb/s热插拔光模块...     

RocketIO的高速串行通道设计与验证

介绍Xilinx公司的Virtex-4 FX系列FPGA中用于解决高速串行互连问题的Rocket IO模块的基本工作原理,并通过开发板验证了该模块在高速数据传输中的可靠性。实验结果表明：该模块的数据传输速率达到3Gb／s,数据传输的误码率在10^-10数量级,传输距离达100cm,可以满足大量数据的实时传输的需要,具有很好的工程应用前景。     

Parallel Optical Packet Address Detection Using Planar Optical Interconnections

We propose a novel planar optical interconnection scheme for 100 Gb/s optical packet address detection, which consists of wave guide grating couplers and a diffractive microlens integrated on a glass substrate 3-dimensionally. Length and duty cycle of the grating couplers have been determined on the bases of ray-optic propagation-mode analysis in a slab waveguide and of rigorous coupled-wave diffraction analysis for out-coupled radiation-modes. The 3-dimensionally integrated planar optics makes it possible to connect each address bit-signal of the TE₀-waveguide mode to the detector with a power uniformity of 6.4% and a total coupling efficiency of 72.3%.     

基于XAUI协议的10 Gb/s光纤通信系统

为提高光纤通信系统的数据吞吐量,增加系统集成度,提出基于附加单元接口(XAUI)协议的10 Gb/s光纤通信系统的设计方法。采用Virtex-5 FPGA内置RocketI/O收发器的通道绑定技术实现用户逻辑至光模块之间的数据通路。利用FPGA及XPAK光模块使以往复杂、高成本的高速光纤通信系统得到简化。     

片上光网络:一种新型片上互连网络

随着单个芯片上集成的处理器的个数越来越多,传统的电互连网络已经无法满足对互连网络性能的需求,需要一种新的互连方式,因此光互连网络技术应运而生.目前,电互连的片上网络在功耗、性能、带宽、延迟等方面遇到了瓶颈,而光互连作为一种新的互连方式引用到片上网络具有低损耗、高吞吐率、低延迟等无可比拟的优势.本文主要探讨了片上光网络的...     

Energy efficiency analysis of high speed triple-play services in next-generation PON deployments

In this paper, the energy consumption of high speed access services up to 1 Gb/s per customer is estimated for different passive optical network (PON) technologies. While other studies on PON power consumption typically assume a fixed split ratio, we also consider a greenfield approach, where the split ratio can be optimized for each technology, taking full advantage of its capacity and reach. The split ratio optimization takes into account Quality of Service (QoS) in terms of bandwidth availability and packet loss for triple-play services (voice, television and Internet). This paper includes an in-depth discussion of our split ratio dimensioning approach and our power consumption model for an optical access network in a major city. The obtained results show that statistical gain provided by dynamic bandwidth allocation as well as power splitting ratio optimization in PONs are key factors for achieving energy efficiency. For access rates up to 900 Mb/s, XG-PON1 turns out to be the most energy efficient option. For higher access rates up to 1 Gb/s, the optimal technology depends on split ratio restrictions. If an existing optical distribution network (ODN) with split ratio 1:64 is used, XG-PON1 remains the most energy efficient technology. If higher split ratios up to 1:256 can be achieved, TWDM PON becomes the most energy efficient solution for access rates up to 1 Gb/s.     

RHiNET-2/SW: a high-throughput, compact network-switch using 8.8-gbit/s optical interconnection

We have developed a high-throughput, compact network switch (the RHiNET-2/SW) for a distributed parallel computing system. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are integrated on a compact circuit board. To realize high-throughput (64 Gbit/s) and low-latency network, the SW-LSI has a customized high-speed LVDS I/O interface, and a high-speed internal SRAM memory in a 784-pin BGA one-chip package. We have also developed device implementation technologies to overcome the electrical problems (loss and crosstalk) caused by such high integration. The RHiNET-2/SW system enables high-performance parallel processing in a distributed computing environment. Shinji Nishimura: He is a researcher in the Department of Network System at the Central Research Laboratory, Hitachi Ltd., at Tokyo. He obtained his bachelors degree in Electronics Engineering from the University of Tokyo in 1989, and his M.E. from the University of Tokyo in 1991. He joined a member of the Optical Interconnection Hitachi Laboratory from 1992. His research interests are in hardware technology for the optical interconnection technologies in the computer and communication systems. Katsuyoshi Harasawa: He is a Senior Enginner of Hitachi Communication Systems Inc. He obtained his bachelors degree in Electrical Engineering from Tokyo Denki University. He is a chief of development of the devices and systems for the optical telecommunication. He was engaged in Development of Optical Reciever and Transmitter module. He joined RWCP project from 1997. His research interests are in hardward technology for optical interconnection in distributed parallel computing system (RHiNET). Nobuhiro Matsudaira: He is a engineer in the Hitachi Communication Systems, Inc. He obtained his bachelors degree in Mercantile Marine Engineering from the Kobe University of Mercantile Marine in 1986. He was engaged in Development of Optical Reciever and Transmitter module at 2.4 Gbit/s to 10Gbit/s. He joined RWCP project from 1998. His reserch interests are in hardware technology for the optical interconnection technology in the computer and communication systems. Shigeto Akutsu: He is a staff in Hitachi Communication Systems Inc. He obtained his bachelors degree in Electronics from Kanagawa University, Japan in 1998. His research interests are hardware technology for the optical interconnection technology in the computer and communication systems. Tomohiro Kudoh, Ph.D.: He received Ph.D. degree from Keio University, Japan in 1992. He has been chief of the parallel and distributed architecture laboratory, Real World Computing Partnership since 1997. His research interests include the area of parallel processing and network for high performance computing. Hiroaki Nishi: He received B.E., M.E. from Keio University, Japan, in 1994, 1996, respectively. He joined Parallel & Distributed Architecture Laboratory, Real World Computing Partnership in 1999. He is currently working on his Ph.D. His research interests include area of interconnection networks. Hideharu Amano, Ph.D.: He received Ph.D. degree from Keio University, Japan in 1986. He is now an Associate Professor in the Department of Information and Computer Science, Keio University. His research interests include the area of parallel processing and reconfigurable computing.     

I/O互联技术及体系结构的研究与发展

I／O互联技术及体系结陶正在发生重大变革,相继涌现了一系列新兴高性能I／O互联技术,包括PCIExpress、RapidIO、HyperTransport以及InfiniBand。该文对它们分别予以研究介绍,针对各自的体系结构、技术特性和应用领域,分别提出了一种合理的系统结构方案。并对这几种I／O互联技术的主要技术特性进行了简要而全面的比较,分析了I／O互联技术及体系结构的现状与发展趋势。     

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure

A multiphase LC voltage-controlled oscillator(VCO) with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery(CDR) circuit for 40 Gb/s optical communications system.Compared with the traditional eight-phase oscillator,this capacitive coupling structure can decrease the number of inductors to half and only of four inductors.The VCO is designed and taped out in TSMC 65 nm CMOS technology.Measurement results show the phase noise is 105.95 dBc/Hz at 1MHz offset from a carrier frequency of 10 GHz.The chip area of VCO is 480 μm×700 μm and the VCO core power dissipation is 4.8 mW with the 1.0 V supply voltage.