A new defect distribution metrology with a consistent discreteexponential formula and its applications

We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since the number of defects is countable (discrete distribution should be used) and analyzed in terms of nondefective chip yield, the g-pdf cannot be used because of its inaccuracy in the near defect-free condition. A discrete exponential pdf is introduced corresponding to the defect count distribution. In addition, a convolution formula of the new pdf is derived statistically which can express realistic defect count distribution with multiple defect sources. It is noted that the popular negative binomial yield formula (NBYF) is directly derived with the convoluted discrete exponential distribution, which interprets the cluster factor given in NBYF as the number of different defect sources predicted. It is experimentally proven that defect count distributions are approximated by this new model within an average error of about 0.01 defects per wafer from film deposition process data     

Some considerations in the formulation of IC yield statistics

Some published modifications of the Poisson distribution for describing IC yield are critiqued. It is shown that it is incorrect to obtain an average yield for a non-uniform defect population by integrating, either in the geometrical space or in the density space, the Poisson distribution with some assumed density distribution functions. The correct way, and happily also the simplest way, is to average the yields of regionally partitioned subpopulations in a discrete manner. The simple Poisson distribution would become rigorously correct when the size of an imaginary IC increases to one quarter of a wafer, regardless of the non-uniformity in defect density. It is also shown that both cases of clustering of defects, one due to interaction among defects themselves, and the other due to wafer regional preference, result in increased yield for a given defect density in a wafer. On the other hand when there are interactions between defects and IC active area elements, or when defects themselves have physical dimensions, there would be a decreased yield for a given defect density, and a non-zero intercept in the plot of the logarithm of yield vs the active device area.     

Yield optimization of modular and redundant multimegabit RAMs: astudy of effectiveness of coding versus static redundancy using thecenter-satellite model

To determine the optimal redundancy organization for yield enhancement, redundant and modular memories are analyzed using the center-satellite model. The model suggests that the degree of redundancy for a memory module be determined according to its distance from the periphery of the wafer since the defect density increases as the periphery is neared. Analytical expressions are formulated for the yield of memory modules with extra rows and/or extra columns, coding, and coding with extra rows. Results from the analysis suggest that, for high levels of defect densities, coding can be more effective than simple extra rows and columns. For high levels of defect densities, coding with extra rows is shown to offer even better yield. For low levels of defect densities, though, just extra rows and columns may be sufficient for a high yield. An optimal amount of redundancy can be found to achieve the highest possible yield using the model that considers precise cluster distributions on the wafer, defects in a cluster, and the radial variation of these defects     

硅片缺陷粒径分布的分形特征及动力学模型

本文研究硅片上与光刻工艺相关的尘粒的粒径分布，分析缺陷粒径分布的分形特征，利用缺陷粒径的分布函数得到缺陷粒径体系的分维数，建立缺陷粒径分布的分形模型，同时给出此模型所得参数的物理意义。最后，本文对缺陷粒径变化过程给出了新的动力学模型，并对此进行分析和讨论。揭示光刻缺陷的粒径分布及其动力学成因，为集成电路可制造性设计及功能成品率的精细表征开辟了一条新径。     

Defect cluster analysis for wafer-scale integration

A methodology for characterizing spatial defect distributions is presented. A correlation function approach providing spatial information not measurable with classical methods such as yield-versus-area curves is described. This additional information includes the spatial extent of defect clustering, the strength of clustering, and uncertainty in clustering magnitude. The correlation function methods are applicable to experimentally determined defect maps or to simulation results based on different assumptions concerning the spatial distribution of defects. It is also shown that the approach is useful in predicting yield for redundant circuit configurations when experimental data pertaining to the spatial distribution of defects are available. This type of yield prediction capability is important for judging the feasibility of various redundancy implementations, including wafer scale integration     

A simulation-based semiconductor chip yield model incorporating a new defect cluster index

This paper proposes a new cluster index that utilizes the defect location data on a wafer in terms of the coefficient of variation. The proposed cluster index is independent of the chip area and does not require assumptions on the distribution of defects. An extensive simulation is performed under a variety of cluster patterns and a yield prediction model is derived through the regression analysis to relate the yield with the proposed cluster index and the average number of defects per chip. The performance of the proposed simulation-based yield prediction model is compared with that of the well-known negative binomial model.     

Yield challenges in wafer stacking technology

Wafer stacking technology offers a higher performance in a smaller size with a lower cost option for microelectronic industries. However, it suffers from a compound yield loss which becomes a key challenge and a limiting factor in this technology. A compound yield loss in wafer stacking has been analyzed and yield challenges have been presented. Assuming a random defect density per wafer and no yield fallout from stacking processes, the compound yield of a bonded wafer pair has been estimated with the most commonly used yield model. As a result, it is proposed that a die area reduction for wafer stacking is needed in order to offer a great yield advantage. Both wafer testing and wafer size are also proven to influence significantly a die yield in a bonded wafer pair.     

The binomial test: a simple tool to identify process problems

The yield distribution of a batch of wafers is an indicator of the type and behavior of defect sources in the manufacturing process. In a stable process, defects generated by these sources are evenly and randomly distributed, repetitive from wafer-to-wafer. The yield distribution of wafers manufactured in such an environment follows the binomial distribution. If, on the other hand, wafers contain defects with systematic patterns that repeat from wafer-to-wafer, the yield distribution tends to be narrower than the binomial distribution. For defect sources that generate systematic wafer-to-wafer variations, the yield distribution widens if compared with the binomial distribution. The binomial distribution can be calculated from the mean yield and the number of dice per wafer. Thus, comparing the actual yield distribution with the corresponding binomial distribution (binomial test) gives the yield improvement engineer a simple first-order indicator of the behavior of defect sources. Since wafer yield data is routinely available from functional production tests, the binomial test can be performed with existing data. This paper describes the principle and use of the binomial test using visual analysis on graphical yield plots of simulated and actual production wafers     

How to extract defect densities from distribution

A technique is presented for representing a defect density, such as might be found on an integrated circuit. Distributions are a powerful tool for presenting defect distributions for test structures and are convenient for yield analysis and modeling. How the concept of distribution can be extended to give more information on the defects is shown. The power of this approach derives from its invariability to test stricture geometry, which enables direct comparison of data from different structures. It is explained how and why defect distributions measured on test structures can be related to those of other structures, i.e. integrated circuits. The mathematics are simple and lead to a defect density which can be expressed in units of defects per geometric factor per independent variable     

硅片Map图信息的提取和利用

分析了硅片Ｍａｐ图所提供的生产成品率和各类不合格芯片的位置分布信息，讨论了利用硅片之间Ｏｖｅｒｌａｐ法（重叠法）和硅片上Ｗｉｎｄｏｗ法（窗口法）对Ｍａｐ图进行的统计。着重讨论了：按硅片中不合格芯片密度的显著差异划分边缘区及中心区；不合格芯片局部聚集现象的定量表示；随机性强的不合格芯片的统计分布；有关信息由相应Ｃ语言软件自动提取，与Ｍａｐ图计算机测试进行联用，可用于生产监控、影响成品率因素分析和工艺缺陷的深入研究。     

Yield degradation of integrated circuits due to spot defects

Economy of integrated circuit fabrication in the presence of quasi-randomly distributed spot defects is described. The distribution of the defects is represented in terms of density and modeled as follows : 1) they are randomly distributed within a limited area; 2) the density in a wafer changes concentrically; and 3) the density is normally distributed from wafer to wafer with uniform deviation throughout a wafer. The yield degradation phenomenon due to such defects has been analyzed using a computer simulation technique. The effect of density variations in a wafer and between wafers has been mainly investigated. An extensive numerical study leads to the following conclusions. 1) The deviation of the yield versus chip-area relation from the simple exponential law is influenced more greatly by the nonuniform defect distribution in a wafer than by the density variation between wafers. 2) The increase of average yield due to the density variation between wafers is sometimes offset by the decrease of the accuracy in yield prediction. Process stabilization is essential for the economical production of a few large-scale chips.     

Interval estimates for yield modeling

Follows statistical convention by calling estimates point estimates. Defect density is a random phenomenon; thus a function of defect density, namely yield, will also be a random variable. An analysis is proposed of the yield model that allows calculation of interval bounds for yield, based on flexible defect models. An examination is also made of the interval estimates for yield from an individual wafer, and the confidence intervals for average yield for a given type of wafer.     

Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions

A hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution and the compound binomial distribution are treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. With respect to applications, hierarchies of yield means and yield probability-density functions are considered and an in-process measure of yield loss is introduced. It is shown that the hierarchical approach naturally embraces the Bayesian approach.     

An Alternative Integrated-Circuit Yield Model

This paper develops a model to predict the number of good integrated circuits (the yield) from a semiconductor wafer processing line. The model is different from other published models and predicts observed outcomes better. Many models tend to predict lower yields than those actually achieved because those models are inherently incapable of predicting the average number of good chips per wafer. The model developed in this paper is based on combinatorial analysis and considers the number of die sites on the wafer and the total number of yield detracting defects on the wafer. In contrast the other models referenced require at least two parameters as input data: the area of one die site or chip and the average defect density. A third parameter, the Cdf of the defect density is often implied by the selection of the model.     

Reliability versus yield and die location in advanced VLSI

The results of multiple correlations between reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures.The model that reliability defect density is proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.     

The nature of defect patterns on integrated-circuit wafer maps

The history of IC-yield models dates from those based on the simple Poisson distribution to current models based on the families of compound and generalized Poisson distributions. The latter are more complex because the IC chips have grown larger in area and circuit density, thereby unveiling the clustering (aggregation) properties of defects on wafers. These clustering properties are reflected by the parameters of the distributions on which the existing yield models are based. The possibility of any statistical distribution providing an exact representation of some actual population is very small. It is important, though, that the parameters of alternative statistical distributions describing some actual population should have some physical meaning. This paper considers 3 distributions used to model empirical defect distributions in IC manufacturing. The applicability of these distributions depends strongly on the area of the chips fabricated on a wafer. The authors discuss the cases where a study of the parameters alone might not provide conclusive evidence about the spatial properties of defect patterns on IC-wafer maps. They propose some measures to explain defect clustering: variance/mean ratio, turning point, mean crowding, and patchiness. Due to the complementary nature of these measures, no measure, by itself, can provide sufficient information about defect patterns or complete details of the differences between several patterns. It is therefore instructive to analyze defect patterns by as many measures as feasible     

Poisson process and integrated circuit yield prediction

Initial integrated circuit yield predictions were overly pessimistic because the assumption that defects were a homogeneous random population led to the logarithm of yield linearly declining with increasing chip area. In reality, the yield vs area curve is concave up, which can be successfully modeled by partitioning the wafer into several Poisson subareas of different defect densities. Previously, this partitioning was done by “eye”. Here an algorithm has been developed to do the partitioning. Good results over a wide range of yields have been obtained. For the particular data presented, the yield curves in the range of interest can be described by a negative binomial distribution, which implies the underlying defect density is governed by the gamma distribution. As previously anticipated, both led to overpredictions of the yield for large chip areas.     

In-line defect sampling methodology in yield management: anintegrated framework

In this paper we provide an integrated framework for designing the optimal defect sampling strategy for wafer inspection, which is crucial in yield management of state-of-the-art technologies. We present a comprehensive cost-based methodology which allows us to achieve the trade-off between the cost of inspection and the cost of yield impact of the undetected defects. We illustrate the effectiveness of our methodology using data from several leading fablines across the world. We demonstrate that this work has already caused a significant change in the sampling practices in these fablines especially in the area of defect data preprocessing (declustering), in-line defect based yield prediction, and optimization of wafer inspection equipment allocation     

A Novel Wafer-Yield PDF Model and Verification With 90–180-nm SOC Chips

In this paper, we describe a new wafer-yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.      

集成电路硅片上缺陷空间分布的分形表征

本文主要研究集成电路硅片上缺陷的空间分布，在详细考察缺陷空间成团效应的基础上，提出了一个新的描述缺陷空间分布的量－分数维，并建立了一个结构化的模型。用分数和维对缺陷的成团效应及其空间分布进行详细地分析和计算机模拟，并验证了结果的正确性。本文为实现集成电路可制造性设计中的功能成品率精确表征奠定了基础。