Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

一种基于刻蚀的SOI深槽介质隔离工艺

介绍了一种基于刻蚀的SOI深槽介质隔离(DTI)工艺。该工艺采用BOSCH刻蚀、兆声清洗、多晶硅回填、刻蚀平坦化等技术,制作流程简单。其介质隔离击穿电压可以根据电路的需要进行调整,并可根据氧化层厚度进行预测。其介质隔离漏电流极低。     

SOI电路窄沟槽隔离技术研究

文章利用SOI材料片做衬底,开展了SOI电路窄沟槽隔离技术的研究,解决了窄槽刻蚀、多晶硅回填、平整化等技术难题,获得了优化的SOI电路窄沟槽隔离工艺技术条件;岛与岛之间的隔离击穿达到300 V,为下一步研制生产SOI电路打下了坚实的基础.     

屏蔽槽SOI高压器件新结构和耐压机理

提出具有屏蔽槽的SOI高压器件新结构和自适应界面电荷耐压模型.该结构在屏蔽槽内产生跟随漏极电压变化的界面电荷,此电荷使埋层介质的纵向电场增加,同时使顶层硅的纵向电场降低,并对表面电场进行调制,因此屏蔽了高电场对顶层硅的影响.借助二维器件仿真研究器件耐压和电场分布与结构参数的关系.结果表明,该结构使埋氧层的电场从传统的3Es升高到近600V/μm,突破了传统SOI器件埋氧层的耐压值,大大提高了SOI器件的击穿电压.     

基于TCAD的绝缘体上硅器件总剂量效应仿真技术研究

绝缘体上硅（Silicon-on-Insulator,SOI）器件的全介质隔离结构改善了其抗单粒子效应性能,但也使其对总剂量效应更加敏感.为了评估SOI器件的总剂量效应敏感性,本文提出了一种基于TCAD （Technology Computer Aided Design）的总剂量效应仿真技术.通过对SOI器件三维结构进行建模,利用TCAD内置的辐射模型开展瞬态仿真,模拟氧化层中辐射感应电荷的产生、输运和俘获过程,从而分别评估绝缘埋层（Buried Oxide,BOX）和浅沟槽隔离（Shallow Trench Isolation,STI）氧化层中辐射感应陷阱电荷对器件电学性能的影响.基于该仿真技术,本文分别研究了不同偏置、沟道长度、体区掺杂浓度以及STI形貌对SOI MOSFET器件总剂量辐射效应的影响.仿真结果表明高浓度的体区掺杂、较小的STI凹槽深度和更陡峭的STI侧壁将有助于改善SOI器件的抗总剂量效应性能.     

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

An ultra-low specific on-resistance(R_on,sp) silicon-on-insulator（SOI） double-gate trench-type MOSFET （DG trench MOSFET） is proposed.The MOSFET features double gates and an oxide trench:the oxide trench is in the drift region,one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide.Firstly,the double gates reduce R_on,sp by forming dual conduction channels.Secondly,the oxide trench not only folds the drift region,but also modulates the electric field,thereby reducing device pitch and increasing the breakdown voltage（BV）.A BV of 93 V and a R_on,sp of 51.8 mΩ·mm² is obtained for a DG trench MOSFET with a 3μm half-cell pitch.Compared with a single-gate SOI MOSFET（SG MOSFET） and a single-gate SOI MOSFET with an oxide trench（SG trench MOSFET）,the R_on,sp of the DG trench MOSFET decreases by 63.3%and 33.8% at the same BV,respectively.     

高性能模拟集成电路工艺技术

介绍了模拟集成电路工艺的发展过程和现状，讨论了国内的BiCMOS工艺、互补双极工艺(CB)、和SOI双极工艺的最新进展。重点介绍了BiCMOS工艺的研完与开发，指出了模拟集成电路工艺的发展趋势。     

用深反应离子刻蚀和介质填充技术制造具有高深宽比的超深电隔离槽

提出了一种利用深反应离子刻蚀(DRIE)和电介质填充方法来制造具有高深宽比的深电学隔离槽的新型技术.还详细讨论了DRIE刻蚀参数与深槽侧壁形状之间的关系,并作了理论上的阐述.采用经过参数优化的DRIE刻蚀深硅槽,并用反应离子刻蚀(RIE)对深槽开口形状进行修正,制造了具有理想侧壁形状的深槽,利于介质的完全填充,避免产生空洞.电隔离槽宽5μm,深92μm,侧壁上有0.5μm厚的氧化层作为电隔离材料.I-V测试结果表明该隔离结构具有很好的电绝缘特性:0～100V偏压范围内,电阻大于1011Ω,击穿电压大于100V.电隔离深槽被首次应用于体硅集成微机械陀螺仪上的微机械结构与电路之间的电气隔离与机械连接,该陀螺的性能得到了显著提高.     

Characterization of the cell leakage of a stacked trench capacitor(STT) cell

The cell leakage of a stacked trench capacitor (STT) cell has been investigated. The major leakage mechanisms of the STT are trench-to-trench leakage, trench junction leakage, and LOCOS isolation leakage. It is shown that compared to a conventional trench capacitor, the trench-to-trench leakage current is reduced and high punchthrough voltage is obtained. Therefore, the trench-to-trench spacing can be reduced 0.1 μm shorter than that of the trench capacitor. These reductions result from the STT structure itself. The surface leakage current, which is the dominant leakage current in the trench capacitor, does not flow in the STT. This paper also describes the effect of the sidewall damage caused by trench etching on the trench junction leakage. Reactive ion etching (RIE) produces deep levels just beneath the trench surface. But, the trench junction of the STT is not influenced by these deep levels because the trench surface is covered by a n^-diffused layer. This paper also investigates the relationship between the cell leakage and the retention time. At DRAM operation temperatures, LOCOS isolation leakage is dominant rather than trench junction leakage. Therefore, the deeper trench can increase the storage capacitance and improve the retention time     

深硅槽开挖工艺

本文介绍了硅槽应用,即硅槽隔离和硅槽电容,对器件性能的改善。并介绍了硅槽隔离和硅槽电容的形成步骤及硅槽刻蚀剖面的形貌控制,CBrF_3刻蚀硅槽侧壁保护层的形成等等。     

Fabrication of Ultra Deep Electrical Isolation Trenches with High Aspect Ratio Using

A novel technique to fabricate ultra deep high aspect ratio electrical isolation trenches with DRIE and dielectric refill is presented.The relationship between trench profile and DRIE parameters is discussed.By optimizing DRIE parameters and RIE etching the trenches’ opening,the ideal trench profile is obtained to ensure that the trenches are fully refilled without voids.The electrical isolation trenches are 5μm wide and 92μm deep with 0.5μm thick oxide layers on the sidewall as isolation material.The measured I-V result shows that the trench structure has good electrical isolation performance:the average resistance in the range of 0～100V is more than 1e11Ω and no breakdown appears under 100V.This isolation trench structure has been used in fabrication of the bulk integrated micromachined gyroscope,which shows high performance.     

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.     

部分局域电荷槽SOI高压器件新结构

提出了部分局域电荷槽SOI(partial locating charge trench SOI,PTSOI)高压器件新结构.该结构在槽内产生随漏极电压变化的界面电荷,此电荷使埋氧层纵向电场从传统的3Esi,C升高到接近SiO2的临界击穿电场Esio2,c;另外,硅窗口将耗尽层引入衬底,因而提高了器件的击穿电压.同时,硅窗口的存在大大缓解了自热效应.借助二维器件仿真研究了器件的击穿特性和热特性.结果表明,漂移区厚2μm,埋氧层厚1μm的PTSOI耐压可达700V以上;对埋氧层厚1μm和3μm的PTSOI,其器件的最高温度分别比TSOI低6K和25K.     

深亚微米隔离技术--浅沟槽隔离工艺

研究了浅沟槽隔离(STI)工艺的各主要工艺步骤:沟槽的形成、沟槽顶角的圆滑、沟槽填充以及化学机械抛光平坦化.使用器件模拟软件Medici和Davinci分析了STI结构的隔离性能以及沟槽隔离MOSFET的Kink效应和反窄宽度效应.     

Hot-carrier degradation behavior of thin-film SOI nMOSFET withisolation scheme and buried oxide thickness

Hot-carrier degradation behavior of thin-film SOI (silicon-on-insulator) nMOSFETs with various isolation techniques and buried oxide (BOX) thickness has been investigated focused on the stress behavior in the SOI structure. LOCOS (local oxidation of silicon) and STI (shallow trench isolation) processes are used as isolation techniques. Buried oxide thickness is 100 and 400 nm, respectively. From the isolation point of view, STI-processed SOI devices have better hot-carrier immunity than LOCOS-isolated SOI devices. In terms of BOX thickness, the thick BOX case has better hot-carrier degradation characteristics than the thin one. It is found that STI process and thick BOX cases induce smaller stress than LOCOS process and thin BOX cases, resulting in better hot-carrier immunity     

A study of trenched capacitor structures

Trenched structures have been fabricated using a highly anisotropic low ion energy bombardment etching technique and evaluated using their CV characteristics. It is shown that the structure can be modeled by two capacitors in parallel, one for the bottom and the other for the sidewall. Obtained results indicate that the crystal orientation of the side and bottom surfaces of the trench determine the value of Nf, fixed charge, and oxide thickness, especially in the thin range. Orientation-dependent oxidation rates account for the different oxide thicknesses on the sides and bottoms of the trenches. Both the value of Nfand the oxide thickness on each wall determine the flat-band voltage Vfbof the corresponding capacitors so that the overall capacitance behavior is given by the relative importance of the side and bottom components. A lower value of Nfthan previously reported is found with the etching technique used. It is also shown that an improvement of Nfcan be obtained by aligning the trench sidewall along 〈100〉 plane.     

槽栅型SiC MOSFET器件单粒子响应特性研究

利用TCAD Sentaurus模拟仿真软件,研究分析了三种不同结构的槽栅型1 200 V SiC MOSFET单粒子响应特性,器件包括传统单沟槽MOSFET、双沟槽MOSFET和非对称沟槽MOSFET结构。仿真结果表明,双沟槽MOSFET的抗单粒子特性优于其它两种结构器件。通过分析可知,双沟槽MOSFET结构的优越性在于有较深的源极深槽结构,有助于快速收集单粒子碰撞过程产生的载流子,从而缓解大量载流子聚集带来的内部电热集中,相比其它两种结构能有效抑制引起单粒子烧毁的反馈机制。     

The effects of etching and deposition on the performance and stress evolution of open through silicon vias

The effects of silicon etching using the Bosch process and LPCVD oxide deposition on the performance of open TSVs are analyzed through simulation. Using an in-house process simulator, a structure is generated which contains scalloped sidewalls as a result of the Bosch etch process. During the LPCVD deposition step, oxide is expected to be thinner at the trench bottom when compared to the top; however, additional localized thinning is observed around each scallop. The scalloped structure is compared to a structure where the etching step is not performed, but rather a flat trench profile is assumed. Both structures are imported into a finite element tool in order to analyze the effects of processing on device performance. The scalloped structure is shown to have an increased resistance and capacitance when compared to the flat TSV. Additionally, the scalloped TSV does not perform as well at high frequencies, where the signal loss is shown to increase. However, the scallops allow the TSV to respond better to an applied stress. This is due to the scallops’ enhanced range of motion and displacement, meaning they can compensate for the stress along the entire sidewall and not only on the TSV top, as in the flat structure.     

Influences of silicon-rich shallow trench isolation on total ionizing dose hardening and gate oxide integrity in a 130 nm partially depleted SOI CMOS technology

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes.     

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.