Investigation of radiated susceptibility during EFT tests

The aim of this paper is to focus on a problem: during an electrical fast transient (EFT) conducted susceptibility test, a very strong radiated field is produced and a radiated coupling with the internal circuitry of the equipment under test (EUT) occurs. Therefore in case of EUT malfunctions, it is difficult to understand whether the resulting failures are due to the injected conducted current (requiring a filtering action) or to the impinging radiated EM field (requiring a shielding action). A model to describe the EM radiation, coming from the current flowing along the EUT power cord, is presented as well as its experimental validation     

利用扩频技术减少高速时钟电路的电磁干扰

数字电子设备的运行速度越来越快,其时钟频率就越来越高,时钟电路产生的辐射干扰就越为严重。本文介绍了一种对抑制时钟电路辐射干扰较为有效的方法-时钟扩频技术。     

电子镇流器电磁干扰抑制措施

介绍了传导干扰、辐射干扰及谐波干扰对电子镇流器的影响,针对抑制辐射干扰和电流谐波畸变产生的干扰,分别给出了有效的抑制措施,并对抑制传导干扰所采取的合理接地、加去耦电路以及采用无源滤波器等措施进行了详细分析。     

静止式电能表射频电磁场辐射抗扰度试验整改

在对一款典型性单相静止式电能表电流采样信号输入端进行增加瓷片电容、串联磁珠和电流采样信号短路等试验和分析的基础上,总结提出一些针对射频电磁场辐射抗扰度试验的解决方案,整改后的电能表通过了射频电磁场辐射抗扰度试验。     

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

A new silicon controlled rectifier (SCR)-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance is proposed. The circuit function to detect positive or negative electrical transients during system-level electrostatic discharge (ESD) and electrical fast transient (EFT) tests has been verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of system-level electrical transient disturbance events. The detection results can be cooperated with firmware design to execute system recovery procedures, therefore the immunity of microelectronic systems against system-level ESD or EFT tests can be effectively improved.     

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.     

煤矿井下水泵电机辐射电磁骚扰测试研究

煤矿井下由于高压、大功率机电设备众多,启停频繁,导致井下电磁干扰严重。本文针对井下电机类 设备的辐射电磁骚扰,分析了旋转电机的电磁兼容辐射发射限值,以及井下实验测试要求和方法,并对井下水泵电 机的辐射电磁骚扰进行了现场测试。测试结果表明:水泵电机在正常稳定运行时的辐射电场较弱,在整个测量频段 内没有明显的噪声突起;在电动机启停阶段,辐射电磁骚扰较强,辐射频谱达到2 GHz,主要辐射频谱在500 MHz 以 内,尤其在频段1 ~10 MHz 之内辐射电场强度达到最大。因此,煤矿井下工频电源驱动的电动机类设备的辐射电磁 骚扰主要是启停阶段产生的瞬态辐射干扰,稳定运行时辐射电磁骚扰对井下电磁环境的影响较小。     

An ECL to CMOS level converter with complementary bipolar outputstage

A novel circuit scheme for the fast amplification of digital signals is presented. A fully complementary bipolar output stage realizes small delay and steep output signal slopes. The improved performance is achieved by intentionally saturating the bipolar output transistors, which allows one to supply the maximum current to the output. We evaluate the performance of saturated bipolar transistors fabricated on bulk silicon. Compared to known circuit schemes, the proposed circuit shows significantly reduced total delay and power dissipation. The driving capability for large capacitive loads is improved. Samples produced in a 2 μm-BiCMOS technology verify the simulated performance     

Assessment of digital integrated circuit electromagnetic emissionbased on radiated power evaluation

This paper deals with the assessment of digital integrated circuit (IC) electromagnetic emission (EME), and concentrates on the specific aspect of EME of long external wiring, driven by IC input-output pins. In particular, the contribution of single IC pins is investigated by analyzing the structure composed of an IC output driver connected via a microstrip line to a receiver. A transmission-line model is used, and an approach based on the concept of radiated power is applied to the characterization of single-pin IC EME in terms of external-wiring radiation effects. By the analysis of typical driver-wiring configurations, it is shown that the spectrum of the driver output current is the quantity of interest, and that the use of wiring with smaller characteristic impedance leads to larger radiated power. The use of a specific test setup (IEC 61967-4-150-Ω direct coupling method) for the experimental assessment of single pin IC emissions is also considered. Frequency-dependent setup effects are experimentally ascertained via a scattering parameter characterization, and definition of suitable circuit functions. An estimate of the degree of correlation between voltage measurements foreseen by the test procedure and the total power radiated by the loading network of an IC driver is derived     

电子装备数字电路板自动检测仪设计

摘要：针对某电子装备数字电路板设计自动检测仪,采用单片机＋FPGA的技术方案,包括信号发生、信号采集、与上位机的USB通信以及连接被测板的接插件四大模块。对不同测试对象输入输出间的差异具有柔性适应能力,无须手工配线,操作简单。由上位PC机驱动运行,测试过程自动化程度高,可在1min内完成单板故障检测。     

A Power Conditioning Stage Based on Analog-Circuit MPPT Control and a Superbuck Converter for Thermoelectric Generators in Spacecraft Power Systems

A thermoelectric generator (TEG) is a very important kind of power supply for spacecraft, especially for deep-space missions, due to its long lifetime and high reliability. To develop a practical TEG power supply for spacecraft, a power conditioning stage is indispensable, being employed to convert the varying output voltage of the TEG modules to a definite voltage for feeding batteries or loads. To enhance the system reliability, a power conditioning stage based on analog-circuit maximum-power-point tracking (MPPT) control and a superbuck converter is proposed in this paper. The input of this power conditioning stage is connected to the output of the TEG modules, and the output of this stage is connected to the battery and loads. The superbuck converter is employed as the main circuit, featuring low input current ripples and high conversion efficiency. Since for spacecraft power systems reliable operation is the key target for control circuits, a reset–set flip-flop-based analog circuit is used as the basic control circuit to implement MPPT, being much simpler than digital control circuits and offering higher reliability. Experiments have verified the feasibility and effectiveness of the proposed power conditioning stage. The results show the advantages of the proposed stage, such as maximum utilization of TEG power, small input ripples, and good stability.     

A 3–5 GHz low-power high-speed radiated power tuning UWB transmitter

To satisfy the different radiated power requirements for the ultra-wideband (UWB) data transmitting in the implantable electronic devices or the wireless component interconnections, a novel low-power high-speed UWB transmitter with radiated power tuning was proposed. The tunable radiated power is achieved by a UWB RF buffer with a peak value controller. The designed low-complex narrow pulse generator and digital ring on–off VCO ensure a high speed transmitting. The low power is realized by using a subtractor to eliminate the base-band component from the output of the VCO and making the UWB RF buffer and the VCO operating in standby mode. The design was fabricated by a standard 0.18 μm CMOS technology. The test results show that the design can achieve maximum data-rate of 250 Mbps, frequency bandwidth from 3 to 5 GHz, radiated power tuning from −40 dBm to −60 dBm, low-power of 8 pJ/bit, and small circuit area of 0.18 mm².     

基于ISA总线多通道控制电路的设计

信号分配在测试系统中至关重要,文中依据某型导弹测试设备的要求设计了一基于ISA总线的多通道控制电路。该电路集成了16路光耦隔离输入电路和8路继电器输出电路,可在ISA总线的控制下完成数据信号、指令信号和电源信号的输入输出。实际应用结果表明,该多通道控制电路的信号分配传输频率可达6.5 MHz,完全达到设计要求;该电路按国家军用标准设计定型,在测试领域具有广阔的应用前景。     

Fast-transient susceptibility of a D-type flip-flop

Human electrostatic discharge (ESD) produces a transient current pulse with a very fast risetime, which can be a source of electromagnetic interference in digital devices. The focus of this paper is the radiated susceptibility of D-type flip-flops implemented in various CMOS and TTL logic technologies. A transient impulse was used to simulate the radiated field produced during an ESD event. A synchronized-disturbance testing methodology is developed that allows accurate control of the instant at which the disturbing signal is applied to the data input lines during an operational cycle of the circuit. The study reveals that these devices are susceptible only during certain time intervals during an operational cycle. The particular interval during which a flip-flop is susceptible is dependent on the logic state of the data input line, the implementation technology of the flip-flop, and the amplitude of the disturbing signal. The total width of the susceptibility intervals is a device parameter that can be used to determine the probability that the flip-flop will fail in the presence of random transient interference pulses     

100kJ级多路强电脉冲发生装置的同步精度技术研究

本文介绍了＂多路强电（磁）脉冲发生装置＂同步精度研究采用的每路输出＂储能电容＋同轴脉冲大电流火花开关放电＂型高压脉冲形成电路。用同轴电缆作为传输线将工作部件连接起来,以脉冲气体激光器作为终端负载（或其他负载,如磁脉冲线圈、电水锤等）组成多路相互隔离的强电脉冲充放电路,设计采用＂多路高压纳秒脉冲发生器装置＂进行同步精度触发,使高功率气体激光器的放电系统同时获得多路同步输出的高强电脉冲能量进行激励放电。同步精度装置的实验研究结果表明,多路同步导通强电脉冲能量已超出100kJ级,多路触发脉冲同步精度〈10ns,可为脉冲气体激光器提供更加超强激励触发能量获得高功率激光。     

1GHz以上的辐射骚扰测量

该文分别介绍了1GHz以上有效辐射功率和辐射骚扰场强的测量方法,并给出了在自由空间远场条件下有效辐射功率和辐射骚扰场强之间的转换关系。     

Modeling and Measurement of Radiated Field Emission From a Power/Ground Plane Cavity Edge Excited by a Through-Hole Signal Via Based on a Balanced TLM and Via Coupling Model

A balanced transmission line model (TLM) and via coupling model is proposed for efficient simulation of radiated field emission from a power/ground plane cavity edge, where the radiated field emission is excited by a through-hole signal via in a multilayer package and printed circuit board (PCB). The radiated field emission is simulated and measured with a series of test boards. The simulation agrees fairly well with the measurement confirming the preciseness and usefulness of the proposed model. It is shown that the through-hole signal via is a considerable source of the radiated field emission as well as the signal loss. When the signal trace is switching vertically stacked reference planes, the signal return current path is disconnected at the via and the impedance becomes extremely high. A significant amount of insertion loss and radiated field emission is generated at resonance frequencies of the plane cavity. The effect of a decoupling capacitor fence (De-Cap Fence) at the edge of the board to mitigate the radiated field emission is examined. The proposed model confirms that the De-Cap Fence changes the resonance mode and frequency of the plane cavity, and reduces the radiated field emission     

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.     

A 36 ppm/°C BiCMOS current reference without requiring curvature-compensation

A low temperature coefficient and high precision current reference generator, with simplified current biasing circuit with only four MOSFETs, has been designed using CSMC’s 0.5 μm BiCMOS process. Utilizing source follower and emitter follower as the bandgap reference output stage, a high performance bandgap reference with no Early effect and low output resistance is realized. A one diode-connected circuit is introduced to further simplify the current biasing. Simulation results of the proposed current reference generator indicate that the output current of 2 μA exhibit a variation of 0.5 % over the temperature range of ?40 to 125 °C is achieved. The current reference draws 21 μA from a 5 V supply. Corner and two hundred runs Monte Carlo simulation show that the maximum deviation from the desired value of the reference current are less than 3.05 % and ± 2.6 %, respectively. This high precision current reference generator is intended for Organic LED driver circuits.