High-performance automatic target recognition through data-specificVLSI

Under the Mojave configurable computing project, we have developed a system for achieving high performance on an automatic target recognition (ATR) application through the use of configurable computing technology. The ATR system studied here involves real-time image acquisition from a synthetic aperture radar (SAR). SAR images exhibit statistical properties which can be used to improve system performance. In this paper, the Mojave configurable computing system uses field programmable gate arrays (FPGA's) to implement highly specialized circuits while retaining the flexibility of programmable components. A controller sequences through a set of specialized circuits in response to real-time events. Computer-aided design (CAD) tools have been developed to support the automatic generation of these specialized circuits. The resulting configurable computing system achieves a significant performance advantage over the existing solution, which is based on application specific integrated circuit (ASIC) technology     

A family of user-programmable peripherals with a functional unitarchitecture

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-μm CMOS EPROM process     

The Transmogrifier-2: a 1 million gate rapid-prototyping system

This paper describes the Transmogrifier-2 (TM-2), a second-generation multifield programmable gate array (FPGA) rapid-prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGA's, four I-Cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a nonuniform partial crossbar, that provides a constant delay between any two FPGA's in the system. The TM-2 architecture is modular and scalable, meaning that systems of various sizes can be constructed from copies of the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with edge resolution of 10 ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications     

Mixed analog-digital crossbar-based hardware implementation of sign–sign LMS adaptive filter

Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign–sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed with infinite precision and there is no necessity for the quantization of the input signal. Since the coefficients of the filter are stored in the switches of the crossbar, they can remain unchanged theoretically for an infinite period of time.     

A New Field Programmable Gate Array: Architecture and Implementation

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below 20 Ω. The chip has been fabricated using a 0.8-μm n-well complementary metal oxide semiconductor technology with two layers of metalization.     

以钯作扩散阻挡层——一种多功能线路板表面处理方法

电子工业不断的小型化,数种不同互联技术于线路板上电子零件连接及电接点被应用范畴不断增加。基于此用途,线路板组装垫位需被一层最后表面处理保护,如这最后表面处理层可用于不同互联技术,可被称为多功能表面层。钯是一个艮好的镍扩散阻挡层,故此层膜能抵受如焊接及键接之严酷老化测试条件。其两大优点为具有良好热超声波键接性及于无铅焊料之非常优艮焊接性。从预镀导线架过往多年经验已知即使很薄贵金属钯层及金层已可有保证可靠的金线键接性。从这一知识,沉镍浸钯浸金层膜系统（ENIPIG）被研发出来。此崭新表面处理ENIPIG三种金属镀液需互相配合才能于线路板工艺上达成理想多功能层膜。因着其薄贵金属层膜,相对于其他表面处理,可节省颇大的成本。     

延迟优化的统一可编程互连电路设计和实现

本文设计了一种对可编程逻辑单元CLB和可编程输出单元IOB均具有统一结构的可编程互连电路。通过偏移互连线和回线技术,使得同种可编程互连线的负载分布均匀,保证了可编程逻辑器件FPGA芯片中信号传输的可预测性和规整性;同时,设计过程中对编程点和驱动器电路进行专门的优化设计,减少了5%延时。运用该互连电路到实例FPGA芯片--FDP芯片中,流片后实测数据表明：该可编程互连电路中各种互连线功能正确,可以正确地完成各种信号的互连,整个芯片的延迟统一而且可预测。     

Interconnection of Subsystem Reduced-Order Models in the Electrothermal Analysis of Large Systems

Heat conduction in an electronic device is commonly modeled as a discretized thermal system (e.g., finite element or finite difference models) that typically uses large matrices for solving complex problems. The large size of electronic-system heat transfer models can be reduced using model reduction methods and the resulting reduced-order models can yield accurate results with far less computational costs. Electronic devices are typically composed of components, like chips, printed circuit boards, and heat sinks that are coupled together. There are two ways of creating reduced-order models for devices that have many coupled components. The first way is to create a single reduced-order model of the entire device. The second way is to interconnect reduced-order models of the components that constitute the device. The second choice (which we call the "reduce then interconnect" approach) allows the heat transfer specialist to perform quick simulations of different architectures of the device by using a library of reduced-order models of the different components that make up the device. However, interconnecting reduced-order models in a straightforward manner can result in unstable behavior. The purpose of this paper is two-fold: creating reduced-order models of the components using a Krylov subspace algorithm and interconnecting the reduced-order models in a stable manner using concepts from control theory. In this paper, we explain the logic behind the "reduce then interconnect" approach, formulate a control-theoretic method for it, and finally exhibit the whole process numerically, by applying it to an example heat conduction problem     

基于SRAM配置技术的FPGA测试方法研究

在FPGA的设计生产过程中,FPGA的测试是一个至关重要的环节.分析了基于SRAM配置技术的FPGA的结构组成及FPGA的基本测试方法.针对6000门可编程资源的FPGA,提出了一种基于阵列和长线线与测试CLB以及采用总线测试开关矩阵相结合的方法.该方法较利用与门或门传递错误信息的所需测试配置次数减少了一半,从而加快了测试速度.     

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

Getting aggressive with passive devices

The circuit boards of many mixed-signal and digital systems are now dominated by individually placed discrete passive (DP) components. This article looks at thin-film integrated passives (IPs) as an alternative to DPs in the effort to save board space and improve electrical performance and system reliability. Integrated passive components have been utilized successfully with ceramic substrate technology for over 50 years in the form of thick-film resistive and dielectric firable pastes. However, this considerable infrastructure cannot be transferred to FR4 and flex substrates due to the high firing temperatures required, and these board materials make up the vast majority of interconnect substrates, in consumer and commercial systems. Mmat has been lacking is thin-film IP materials and fabrication processes that are compatible with organic boards     

Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.     

Novel Test Approach for Interconnect Resources in Field Programmable Gate Arrays

A novel test approach for interconnect resources(IRs)in field programmable gate arrays (FPGA)has been proposed.In the test approach,SBs (switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

RF MEMS switch integrated on printed circuit board with metallic membrane first sequence and transferring

This letter reports, for the first time, on RF MEMS switches integrated on flexible printed circuit boards (i.e., FR-4) using transfer technology. The devices were first processed on Si-substrate using a modified MEMS sequence and subsequently transferred onto an FR-4 substrate by thermal compressive bonding, mechanical grinding, and wet removal of silicon. The switches were demonstrated with flat metal membrane (top electrode), precisely controlled gap between the membrane and bottom electrode, low insertion loss (/spl les/ 0.15 dB at 20 GHz), and high isolation (/spl sim/ 21 dB at 20 GHz). This technology shows the potential to monolithically integrate RF MEMS components with other RF devices on organic substrate for RF system implementation.     

Field programmable analog arrays for implementation of generalized nth‐order operational transconductance amplifier‐C elliptic filters

This study presents a new architecture for a field programmable analog array (FPAA) for use in low‐frequency applications, and a generalized circuit realization method for the implementation of nth‐order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA‐C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA‐C symmetric balanced structure for even/odd‐nth‐order low‐pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low‐power designs for implementation of biopotential signal processing systems.     

Resource requirements and layouts for field programmableinterconnection chips

Field-programmable interconnection chips (FPIC's) provide the capability of realizing user programmable interconnection for any desired permutation. Such an interconnection is very much desired for supporting rapid prototyping of hardware systems and for providing programmable communication networks for parallel and distributed computing. An FPIC should realize any possible permutation of input to output pins via a set of programmable switches. In this paper, we show that any such architecture requires a minimum of Ω(n log n) switches, where Ω is the number of I/O pins. The result stems from an analysis of the underlying permutation network. In addition, for networks of bounded degree d, we prove an Ω(log_d-1 n) bound on the routing delay (maximum length of routing paths for specific I/O permutations) and an Ω(n log_d-1 n) bound on the average utilization of programmable switches used by the FPIC to implement a specific permutation. For the same type of networks, we prove an Ω(n log_d-1 n) bound on the number of nodes of the network. Furthermore, we design efficient architectures for FPIC's offering a wide variety of routing delays, high average programmable resource utilization, and O(n²)-area two-layer layouts. The proposed structures are called hybrid Benes-Crossbar (HBC) architectures and clearly exhibit a tradeoff between performance (routing delay utilization) and area of the layout     

Efficient Realization of Parity Prediction Functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.