SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

SiO_2/SiC界面陷阱对SiC MOSFET开关损耗的影响

位于SiO_2/SiC界面处密度较高的陷阱,不仅俘获SiC MOSFET沟道中的载流子,而且对沟道中的载流子形成散射、降低载流子的迁移率,因而严重影响了SiC MOSFET的开关特性。目前商业化的半导体器件仿真软件中迁移率模型是基于Si器件开发,不能体现SiO_2/SiC界面处的陷阱对沟道中载流子的散射作用。通过引入能正确反映界面陷阱对载流子作用的迁移率模型,利用半导体器件仿真软件研究了界面陷阱对SiC MOSFET动态特性的影响。结果表明,随着界面陷阱密度的增加,SiC MOSFET开通过程变慢,开通损耗增加,而关断过程加快,关断损耗减小;但是由于沟道载流子数量的减少、导通电阻的增加,总损耗是随着界面陷阱密度的增加而增加。     

耗尽型4H-SiC埋沟MOSFET器件解析模型研究

建立了基于漂移扩散理论的4H-SiC埋沟MOSFET器件的物理解析模型。SiC/SiO_2界面处的界面态密度及各种散射机制都会导致器件载流子迁移率的下降,采用平均迁移率模型,分析散射机制对载流子迁移率的影响,讨论了界面态对阈值电压的影响。考虑到器件处在不同工作模式下,沟道电容会随栅压的变化而改变,采用了平均电容概念。器件仿真结果表明:界面态的存在导致漏极电流减小;采用平均迁移率模型得到的计算结果与实验测试结果较为一致。     

碳化硅MOSFET反型沟道迁移率的研究

SiC MOSFET是制作高速、低功耗开关功率器件的理想材料，然而，制作反型沟道迁移率较高的SiC MOSFET工艺尚未取得满意结果。通过在N0中高温退火可以显著地提高4H—SiC MOSFET的有效沟道迁移率；采用H2中退火制作的4H—SiC MOSFET阈值电压为3．1V，反型沟道迁移率高于100cm^2／Vs的栅压的安全工作区较宽。N20退火技术由于其的安全性而发展迅速并将取代N0。     

SiO_2/SiC界面对4H-SiC n-MOSFET反型沟道电子迁移率的影响

提出了一种基于器件物理的4 H- Si C n- MOSFET反型沟道电子迁移率模型.该模型包括了界面态、晶格、杂质以及表面粗糙等散射机制的影响,其中界面态散射机制考虑了载流子的屏蔽效应.利用此模型,研究了界面态、表面粗糙度等因素对迁移率的影响,模拟结果表明界面态和表面粗糙度是影响沟道电子迁移率的主要因素.其中,界面态密度决定了沟道电子迁移率的最大值,而表面粗糙散射则制约着高场下的电子迁移率.该模型能较好地应用于器件模拟.     

6.5 kV SiC MOSFET的优化及开关特性

优化设计了电力系统用6.5 kV SiC MOSFET,测得该器件的导通电流为25 A,阻断电压为6 800 V,器件的巴利加优值(BFOM)达到925 MW/cm²。基于感性负载测试电路测试了器件的高压开关瞬态波形。在此基础上,借助仿真软件构建6.5 kV SiC MOSFET芯片级和器件级仿真模型,通过改变器件元胞结构、阱区掺杂浓度、栅极电阻、寄生电感等参数,研究了6.5 kV SiC MOSFET开关瞬态过程和电学振荡影响因素。结果表明,减小结型场效应晶体管(JFET)宽度有利于提高器件dV/dt能力,而源极寄生电感和栅极电阻是引起栅极电压振荡的重要因素。研究结果有助于分析研究6.5 kV SiC MOSFET在智能电网应用中的开关特性,使得基于SiC MOSFET的功率变换器系统具有更低的损耗、更高的频率和更高的可靠性。     

6.5kV,25 A 4H-SiC功率DMOSFET器件

<正>与硅IGBT相比,SiC高压功率DMOSFET器件的导通电阻和开关损耗更低,工作温度更高,在智能电网的应用中具有巨大的应用前景。南京电子器件研究所研制出一款6.5kV25ASiC功率DMOSFET器件。建立了高压SiC DMOSFET仿真模型并开展元胞结构设计,通过采用低界面态密度栅极氧化层制备以及JFET区选择掺杂等先进工艺技术,在60μm厚外延层上制备了6.5 kV SiC DMOSFET,芯片有源区尺寸37 mm~2。该器件击穿电压大于6.9 kV,导通电流大于25 A,峰值有效沟道迁移率为23 cm~2/(V·s),比导通电阻降低到44.3 mΩ·cm~2,缩小了与国际先进水平的差距。     

SiC JFET与SiC MOSFET失效模型及其短路特性对比

建立了两种碳化硅（SiC）器件JFET和MOSFET的失效模型.失效模型是在传统的电路模型的基础上引入了额外附加的泄漏电流,其中,SiC JFET是在漏源极引入了泄漏电流,SiC MOSFET是在漏源极和栅极引入了泄漏电流;同时,为了体现温度和电场强度与失效的关系,用与温度和电场强度相关的沟道载流子迁移率代替了传统电路模型所采用的常数迁移率.有关文献的实验结果和半导体器件的计算机模拟（Technology Computer Aided Design,TCAD）验证了两种SiC器件失效模型的准确性.所建立的失效模型能够对比SiC JFET和SiC MOSFET的短路特性.     

SiO2/SiC界面对4H-SiC n-MOSFET反型沟道电子迁移率的影响

提出了一种基于器件物理的4H-SiC n-MOSFET反型沟道电子迁移率模型.该模型包括了界面态、晶格、杂质以及表面粗糙等散射机制的影响,其中界面态散射机制考虑了载流子的屏蔽效应.利用此模型,研究了界面态、表面粗糙度等因素对迁移率的影响,模拟结果表明界面态和表面粗糙度是影响沟道电子迁移率的主要因素.其中,界面态密度决定了沟道电子迁移率的最大值,而表面粗糙散射则制约着高场下的电子迁移率.该模型能较好地应用于器件模拟.     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

The effect of interface state trap density, D_it, on the current-voltage characteristics of four recently proposed III-V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δ-doping below the channel, a buried channel design with δ-doping, and implant-free quantum-well HEMT-like structure with no δ-doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δ-doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

施主型界面态引起槽栅PMOSFET性能退化的特征

基于流体动力学能量输运模型 ,对沟道杂质浓度不同的深亚微米槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 .研究结果表明同样浓度的界面态密度在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且电子施主界面态密度对器件特性的影响远大于空穴界面态 .特别是沟道杂质浓度不同 ,界面态引起的器件特性的退化不同 .沟道掺杂浓度提高 ,同样的界面态密度造成的漏极特性漂移增大 .     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Advances in SiC power MOSFET technology

In recent years, SiC has received increased attention because of its potential for a wide variety of high temperature, high power, high frequency, and/or radiation hardened applications under which conventional semiconductors cannot adequately perform. For semiconductor devices designed to operate in these harsh conditions, SiC offers an unmatched combination of electronic and physical properties. The availability of SiC wafers on a commercial basis has led to the demonstration of many types of metal-oxide semiconductor (MOS)-gated devices that exploit its unique properties. To which extent the potential of SiC power MOSFET can be utilized is a question of appropriate SiC polytype, device structure, MOS interface quality and maturity of the technology. This paper reviews the present status of the SiC power MOSFETs technology that is approaching commercialization. Emphasis is placed upon the impact of SiO₂–SiC interface quality on the performance of SiC MOSFETs.     

一种考虑复合电流的SiC LBJT行为模型改进

介绍了一种考虑基区SiC/SiO₂界面处复合电流的SiC LBJT改进模型。分析了横向碳化硅双极结型晶体管与其垂直结构之间的区别,将横向BJT的外延层和半绝缘机构等效为衬底电容。再引入一个平行于SiC BJT基极结的附加二极管来描述复合电流,以垂直SiC BJT的SGP模型为基础建立SiC LBJT行为模型。校准了LBJT模型的基区渡越时间,模型与实际器件的开关特性接近吻合。相较于未考虑复合电流的LBJT模型,改进后的模型输出特性曲线与实测数据精度误差较小。该模型可以较精确地描述受复合电流影响的LBJT器件行为。     

单界面陷阱对7 nm P型GAAFET性能影响研究

采用3D TCAD软件仿真分析了单界面陷阱对7 nm P型全环栅场效应晶体管DC和AC性能的影响。研究结果表明:单个陷阱能使转移特性曲线发生严重偏移;当单界面陷阱位于沟道中心附近且陷阱能级靠近导带时,对关态电流和阈值电压的影响最大;陷阱使栅电容的相对变化量小于1%;环栅晶体管沟道长度和纳米线直径的缩小会加重陷阱对器件性能的影响,高介电常数材料的Spacer可减小陷阱引起的沟道能带弯曲程度,从而缓解陷阱对器件性能的影响。在调节器件结构参数使器件性能最大化的同时,应使陷阱对器件性能的影响最小化。     

槽栅功率MOSFET单粒子微剂量效应电荷沉积模型

重离子会在槽栅功率MOSFET器件中引起电压电流特性漂移,即单粒子微剂量效应。为表征该效应,本文提出了一个电荷沉积模型。该模型可用来计算重离子轰击氧化层后引起的电荷沉积及电荷输运过程。应用本模型计算了单个Xe离子在二氧化硅/硅界面沉积的空穴正电荷。通过将该计算结果导入Sentaurus仿真软件中,模拟了单个Xe离子轰击槽栅MOSFET后引起的电压电流曲线漂移。模拟结果与相关实验结果一致。最后,应用本模型研究了不同参数对槽栅功率MOSFET单粒子微剂量效应的影响。     

Study on the degradation induced by donor interface state in deep-sub-micron grooved-gate P-channel MOSFET’s

The degradation of electrical performance induced by interface states is one main reason for failure occurs in deep-sub-micron MOS devices. Especially for grooved-gate MOS devices, there are a large amount of interface states and flaw formed during the etching of concave. Based on the hydrodynamics energy transport model, using MEDICI simulator, the degradation induced by donor interface states is analyzed for deep-sub-micron grooved-gate PMOSFET’s with different channel doping densities and compared with that of corresponding conventional planar PMOSFET’s. The results also compared with that of degradation induced by acceptor interface states. The simulation results indicate that the degradation induced by same interface state density in grooved-gate PMOSFET’s is larger than that in planar PMOSFET’s, and in both structure devices, the impact of electron donor interface states on device performance is far larger than that of hole donor interface state. This work gives an useful insight of mechanism of hot-carrier degradation for grooved gate MOS devices and lays a solid foundation for grooved gate devices used in deep-sub-micron region VLSI practically.     

GaAs/InP键合电学性质的研究

III-V族晶片键合技术对于光电器件的制备和实现光电集成有着重要意义,然而,对于键合界面的电学性质仍然研究较少。采用热电子发射理论,基于界面态能级在禁带中连续分布的假设,根据分布函数结合I-V测试曲线可建立键合结构的界面态计算模型。利用该模型对不同条件下键合的InP/GaAs电学性质做了分析比较,通过初始势垒的确定,计算并比较了各种键合条件下GaAs/InP键合时的界面电荷及界面态密度。实验及计算结果表明疏水处理表面550度条件下键合晶片对有更低的表面初始势垒和更少的界面态密度,因而具有更好的I-V特性。