FPGA implementation of a systems identification module based upon Hopfield networks

The aim of this contribution is to implement a hardware module that performs parametric identification of dynamical systems. The design is based upon the methodology of optimization with Hopfield neural networks, leading to an adapted version of these networks. An outstanding feature of this modified Hopfield network is the existence of weights that vary with time. Since weights can no longer be stored in read-only memories, these dynamic weights constitute a significant challenge for digital circuits, in addition to the usual issues of area occupation, fixed-point arithmetic and nonlinear functions computations. The implementation, which is accomplished on FPGA circuits, achieves modularity and flexibility, due to the usage of parametric VHDL to describe the network. In contrast to software simulations, the natural parallelism of neural networks is preserved, at a limited cost in terms of circuitry cost and processing time. The functional simulation and the synthesis show the viability of the design. In particular, the FPGA implementation exhibits a reasonably fast convergence, which is required to produce accurate parameter estimations. Current research is oriented towards integrating the estimator within an embedded adaptive controller for autonomous systems.     

An FPGA implementation of a neural optimization of block truncation coding for image/video compression

This paper presents a Field Programmable Gate Array (FPGA) implementation for image/video compression using an improved block truncation coding (BTC) image compression technique. The improvement is achieved by employing a Hopfield neural network (HNN) to calculate a cost function upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus resulting in better compression ratios. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The implementation exploits the inherent parallelism of the BTC/HNN algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide a processing speed of about 1.113 × 10⁶ of pixels per second with a compression ratio which varies between 1.25 and 2 bits/pixel, according to the image nature.     

一种改进的伪布尔可满足性算法用于FPGA布线

为了避免伪布尔可满足性算法在布线过程中带来的增加转换成本的负面影响,提出了一种用于FPGA的新的布线算法,该算法结合了伪布尔可满足性算法与几何布线算法的优点。在布线过程中,先选用PathFinder这种几何布线方法对FPC}A进行布线,如果不能成功再采用伪布尔可满足性算法。并在布线流程中增加了静态对称破缺技术对伪布尔约束进行预处理,侦测并破缺其中的对称,从而达到减少搜索路径,消减成本的目的。初步的实验结果表明,这种混合布线方法可以显著减少运行时间,加速求解过程,并且对整体方案无不良影响。     

基于FPGA的图像预处理快速算法及仿真

工程实践中,可编程逻辑器件已经越来越多的受到重视和应用.文中以DSP处理大量数据时,实时性难以达到要求入手,介绍了应用可编程逻辑器件FPGA提高程序效率、实现快速运算的一种方法,并设计了一个利用中值滤波进行图像预处理的系统,之后进行了仿真和实验验证.文章最后得到结论,采用FPGA通过用硬件逻辑来实现运算量大但相对比较简单的算法,效率要大大高于软件的多次循环,若在系统中采用DSP和FPGA合作处理数据,则可以各自发挥长处,实现快速算法.     

Leveraging cost matrix structure for hardware implementation of stereo disparity computation using dynamic programming

Dynamic programming is a powerful method for solving energy minimisation problems in computer vision, for example stereo disparity computations. While it may be desirable to implement this algorithm in hardware to achieve frame-rate processing, a na?¨ve implementation may fail to meet timing requirements. In this paper, the structure of the cost matrix is examined to provide improved methods of hardware implementation. It is noted that by computing cost matrix entries along anti-diagonals instead of rows, the cost matrix entries can be computed in a pipelined architecture. Further, if only a subset of the cost matrix needs to be considered, for example by placing limits on the disparity range (include neglecting negative disparities by assuming rectified images), the resources required to compute the cost matrix in parallel can be reduced. Boundary conditions required to allow computing a subset of the cost matrix are detailed. Finally, a hardware solution of Cox’s maximum-likelihood, dynamic programming stereo disparity algorithm is implemented to demonstrate the performance achieved. The design provides high frame rate (>123 fps) estimates for a large disparity range (e.g. 128 pixels), for image sizes of 640 × 480 pixels, and can be simply extended to work well over 200 fps.     

A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme

A novel video encoder that controls image quality on the fly is presented along with its FPGA implementation. As a result of this new feature, which uses a concept called pruning, the processing speed increases by a factor of two when compared to the conventional method of processing without pruning. The FPGA implementation conforms to MPEG-2 standards and is capable of processing color pictures of sizes up to 1024×768 pixels at the real time rate of 25 frames/s.     

Real-time hardware acceleration of the trace transform

The trace transform is a novel algorithm that has been shown to be effective in a number of image recognition tasks. It is a generalisation of the Radon transform that has been widely used in image processing for decades. Its generality—allowing multiple functions to be used in the mapping—leads to an algorithm that can be tailored to specific applications. However, its computation complexity has been a barrier to its widespread adoption. By harnessing the heterogeneous resources on a modern FPGA, the algorithm is significantly accelerated. Here, a flexible system is developed that allows for a wide array of functionals to be computed without re-implementing the design. The system is fully scalable, such that the number and complexity of functionals does not affect the speed of the circuit. The heterogeneous resources of the FPGA platform are then used to develop a set of flexible functional blocks that can each implement a number of different mathematical functionals. The combined result of this design is a system that can compute the trace transform on a 256 × 256 pixel image at 26 fps, enabling real-time processing of captured video frames.

现场可编程器件的异步串行配置

介绍了可编程集成电路的基本知识，着重介绍了大规模现场可编程集成电路ＦＰＧＡ的编程方案，以Ａｌｔｅｒａ公司的ＦＬＥＸ８０００系列芯片为例，给出了使用单片机和微机的两种配置实例。     

基于FPGA的全数字脉宽调制器

为了解决传统的脉宽调制(PWM)信号电路的设计复杂、噪声大及抗干扰能力差等缺点,设计一种全数字脉宽调制器(DPWM),采用先进的现场可编程逻辑器件(FPGA)和硬件描述语言(VHDL),有效地控制cs时钟信号的上升沿和下降沿和脉冲宽度,可以很好地解决像增强器的光晕现象,扩大其动态范围;通过仿真实验,验证了全数字脉宽调制器(DPWM)控制系统具有控制灵活精确、设计简单易修改、抗噪抗干扰能力强等特点;FPGA可重复擦写,当需要实现其它功能时,只需在程序上改动即可,可方便地嵌入需要调节控制的各个系统,加快系统开发和利用.     

一种专用型无线HUB的FPGA仿真与实现

以实现小型足球机器人无线通信系统单进多出的网络拓扑结构为目的,提出了一种应用于该无线通信系统的专用型无线HUB的FPGA设计与实现.针对该无线HUB的功能需求分析,介绍和讨论了系统的总体架构设计.详述了串口和无线SPI、帧同步、寻址模块、流控和帧处理模块的FPGA设计方法.仿真调试和仔细分析了流控管理单元和帧处理单元的设计.仿真调试的结果和分析说明:该设计逻辑清晰、时序正确,给予通信以充分的保障.     

实时视频数据采集的FPGA实现

介绍一种在工矿监视系统中采用FPGA实现视频数据实时采集和显示的设计方案。系统中采用FPGA和视频解码器实现了高速连续的视频数据采集与处理。处理后的视频信号通过VGA格式转换,可以在现场VGA显示器上观看,也可以通过键控将数据存储在存储介质中,从而实现了实时视频监视。     

基于FPGA的乘法器实现结构分析与仿真

现场可编程门阵列(FPGA)的快速发展为数字信号处理(DSP)系统设计提供了一种新的解决方案，而乘法运算是DSP领域内的一种基本运算，应用极为广泛，对乘法运算基于FPGA的实现结构进行研究具有重要意义。本文分析乘法运算的特点，给出了几种适应FPGA实现的乘法器结构。并在Xilinx公司的ISE 4．1i软件环境下，采用VHDL和VIRELOG硬件描述语言进行了设计实现并对其性能进行了比较分析。     

基于单片机及FPGA的电力载波通信异常信号监测系统设计

为了保证电力载波通信网络的运行安全,以单片机及FPGA为硬件支持,设计基于单片机及FPGA的电力载波通信异常信号监测系统。根据电力载波通信网络的异常原因,设置异常信号特征作为判据。在建立的电力载波通信网络模型下,利用装设的信号采集设备、单片机以及FPGA元件,采集并处理电力载波通信信号。通过实时通信信号的特征提取与匹配,判定当前信号的异常状态,计算得出通信异常信号量和信号异常类型,最终以可视化的形式输出电力载波通信异常信号的监测结果。通过系统测试得出结论：与传统通信异常信号监测系统对比,优化设计系统的通信异常信号量的监测误差降低了1.37dBm,且通信异常信号类型的误检率得到明显降低。     

量程自整定高精度频率测量的FPGA实现

数字频率计是一种应用十分广泛的电子测量仪表,针对宽频率范围被测信号频率测量应用需求,提出并实现了一种基于FPGA的自动量程切换高精度数字频率计的设计方法。通过构建测频控制器、闸门同步生成器、量程自动切换等模块,并采用Verilog HDL语言进行描述,运用自顶向下的数字系统设计方法实现了宽频率范围频率测量的量程自动切换。在Xilinx公司的XUPV5-LX110T开发板上进行了测试,给出了系统后仿真波形。结果表明目标系统能根据被测信号频率范围进行自动量程切换,实现高精度频率测量,测量精度不低于10-7,有效提高系统稳定性和抗电磁干扰能力。     

基于频谱分析的电机故障监测仪硬件研究及FPGA设计

提出了基于知识产权核(IPCore)的快速傅里叶变换(FFT)实现方案,以解决传统电动机故障诊断的非实时性问题。整个设计利用ALTERA公司提供的DSP Builder和QUARTUS Ⅱ 6.0开发软件,根据频谱分析的原理,采用先进的层次化设计思想,利用FFT处理器设计了一种适合在FPGA器件上实现的频谱分析的实用电路,使用一片FPGA芯片完成了整个频谱分析系统的电路设计。整体设计经过时序仿真和硬件仿真,运行速度达到50 MHz以上。结果表明该方法具有设计简单、快速、高效和实时性好等优点,具有一定的通用性和灵活性。     

Design space exploration for partially reconfigurable architectures in real-time systems

In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area improvement up to 38% on some resources without compromising application performance, in a very small amount of time: less than 30 s.     

An embedded multi-core biometric identification system

Biometric identification systems exploit automated methods of recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable as biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for image processing is required. In this paper we propose a parallel architecture that efficiently implements the high computationally demanding core of a matching algorithm based on Band-Limited Phase Only spatial Correlation (BLPOC), performed by two concurrent computational units implemented onto a Stratix II Altera family FPGA. The device here described is competitive with similar hardware solutions described in literature and outperforms the elaboration capabilities of general-purpose processors.     

一种基于FPGA的可配置SPI Master接口设计实现

介绍一种基于FPGA的SPI Master Interface设计。依据SPI同步串行接口的通信协议,设计一个可配置的、高度灵活的SPI Master模块,以满足正常、异常及强度测试要求。利用Verilog语言实现SPI接口的设计原理和编程思想。     

XCP调频波脉冲计数鉴频系统的FPGA实现

为提高XCP中三路调频信号鉴频解调的抗干扰性能,采用脉冲计数式鉴频解调法,鉴频中采用倍频技术,提高了鉴频灵敏度。由参考信号发生器产生正交CQR和同相CIR两个参考信号．利用这两个相互正交的同步信号,并行控制多路脉冲计数器实施数字鉴频。采用现场可编程逻辑门阵列FPGA进行鉴频器硬件电路设计来降低系统复杂度并提高系统稳定性。测试结果表明,系统完全满足精度及可靠性等方面要求。