面向5G通信系统的小型化不等分功分器设计�

针对5G通信设备与测试仪器对微波器件小型化的要求越来越高,无源功分器以工作稳定、结构简单的优势,在各种微波系统中得到了大量的应用。本文设计了一种集总参数小型化π模型不等分的Wilkinson功分器,两个输出端口的功率比为２∶１,相对于传统的结构,在保证性能满足要求的前提下,可以大幅缩小器件的尺寸,具有实际的应用价值。     

一种米波功分器的小型化设计

提出一种半集总参数的Wilkinson功分器的结构原型,介绍功分器设计的原理和方法,并且设计加工了一个VHF波段的功分器,给出了实验结果,验证了本方法的可行性.     

基于SiGe工艺多抽头电感结构的紧凑型Wilkinson功分器

为了解决传统Wilkinson功分器损耗高、尺寸大的问题,从功分器的理论分析出发,将传统的微带线结构和LC集总式结构进行改进,在隔离电阻处引入频率补偿电容,设计一种新型的多抽头电感结构的紧凑型宽带二等分功分器。所设计的功分器基于0.18μm SiGe BiCMOS工艺。射频/微波电磁仿真显示,在8～16 GHz的频带范围内,功分器的分配损耗小于0.8 dB,隔离度大于20 dB,端口回波损耗大于15 dB,核心电路版图面积仅为0.30 mm×0.25 mm,可满足宽带功分器低损耗、小型化、高隔离度的设计要求。     

基于GaAs衬底的功分器芯片设计

依据Wilkinson功分器原理,将四分之一波长传输线等效为集总参数电路,在GaAs衬底上设计并实现一款20～30 GHz宽带功分器芯片。通过工艺线提供的衬底设置和电磁仿真软件建模仿真优化,功分器的测试结果和仿真结果具有较高的一致性。芯片尺寸为0.9 mm×0.7 mm×0.1 mm。探针台在片测试结果表明,功分器芯片在设计带宽20～30 GHz内,插入损耗小于4 dB,隔离度大于20 dB,输入回波损耗和输出回波损耗均优于15 dB,具有低损耗、高隔离、驻波好、面积小、成本低的优良特性。     

UHF波段宽带集总Wilkinson功率分配器的设计

提出了一种基于LTCC技术的UHF波段宽带集总Wilkinson功率分配器。该功分器由LC结构组合而成,根据奇偶模阻抗理论,这样的结构可实现更高的隔离度。采用了螺旋电感结构来实现功分器的小型化。通过ADS电路仿真以及HFSS三维建模设计,功分器的加工测试结果与电磁仿真结果相匹配。功分器的中心频率为1.05 GHz,带宽为300 MHz,两输出端口插入损耗均优于3.26 d B,隔离度优于28 d B(1.08 GHz相似文献   

一种串联式功分器设计

功分器是微波器件中的基本器件,常见的功分器都是用并联电路来实现,由并联电路的特点可知,当功分比较大时,功分器将存在高阻线,这就增加了加工难度,同时也增大功分器的插损,从而限制了并联式功分器在某些领域的使用。文中提出了一种串联式功分器结构设计,给出了等效电路,并对其进行仿真设计,仿真结果表明此方法是有效的。与Wilkinson功分器相比,串联式功分器工程上能够实现较大的功分比,输出相位差为180°,在超宽带巴仑和平面魔T等方面具有潜在的应用价值。     

集总元件宽带Wilkinson功分器的研究

提出了一种集总元件宽带Wilkinson功分器的分析及设计方法。从功分器的奇偶模阻抗理论分析出发,将功分器设计转化为在偶模下求解阻抗比为2:1的宽带阻抗变换和在奇模下求解宽带阻抗匹配的问题,采用LC阻抗变换节取代传统电路的λ/4传输线,减小功分器体积,并推导出两级功分器的元件解算公式。经ADS仿真验证,由解算公式得到的两级功分器,在760～1240MHz的带宽内功率分配损耗小于0.1dB,隔离度大于20dB,输入输出端口反射系数均小于-20dB,可用带宽fH/fL为1.64,实现了Wilkinson功分器小尺寸、带宽大的优点。     

基于改进1-π拓扑结构的螺旋电感可扩展模型

随着射频集成电路空前发展,电感作为射频电路中重要无源器件应用越来越广.目前其仿真模型应用频率范围较窄并且仿真结果与测试结果拟合较差.本文提出了基于0.13μm SOI CMOS工艺的片上螺旋电感修改模型.模型采用了1-π等效电路,包含有表征衬底涡流的RL并联网络并且改进了由趋肤效应引起的金属线圈中涡流的表征.利用数理统计中的回归分析方法,得到扩展模型参数的表达式.制备了13种不同尺寸的片上螺旋电感用于验证模型.本文提出的方法,对不同尺寸的电感在频率达到自谐振频率以上的行为提供了更好的电路解释.     

隔层不交叠多层电感分析与设计

提出了一种隔层不重叠的新型结构片上螺旋电感,其实现工艺与标准CMOS多层布线技术兼容.结合螺旋电感的集总模型,利用电磁场仿真软件HFSS进行了该器件的模拟仿真,与相同结构参数和工艺参数的传统不隔层交叠多层电感相比,提出的新型电感在品质因子、自谐振频率、3dB带宽等性能参数上明显改善,其中电感品质因子提高3.5％,带宽增...     

S波段GaAs高效率线性内匹配HFET研制

介绍了一种基于GaAs HFET结构的S波段内匹配器件的设计方法。由于大栅宽器件模型难以准确确定,提取了具有相似结构的小栅宽器件模型。在ADS设计环境中,利用Load-Pull算法推算出大栅宽器件的管芯阻抗。器件采用两个栅宽为16mm的管芯进行功率合成。对于匹配电路的设计,首先通过一级LC低通滤波网络进行阻抗变换,将每个管芯的阻抗提升到10Ω左右,再通过Wilkinson功分器将阻抗变换到50Ω。电容和功分器采用瓷片加工,电感则通过金丝实现。研制成功的内匹配功率管,其工作频率为2.2～2.5GHz,输出功率P1dB大于20W,功率增益G1dB大于14dB,功率附加效率大于48%。     

Highly miniaturised Wilkinson power divider employing /spl pi/-type multiple coupled microstrip line structure

Using a /spl pi/-type multiple coupled microstrip line structure, a highly miniaturised Wilkinson power divider is fabricated. The line length of the power divider was reduced to about /spl lambda//44, and its size was 37% of a conventional Wilkinson power divider. The novel power divider showed good RF performances in S/C band.     

Miniaturized Wilkinson power dividers utilizing capacitive loading

The authors report the miniaturization of a planar Wilkinson power divider by capacitive loading of the quarter wave transmission lines employed in conventional Wilkinson power dividers. Reduction of the transmission line segments from λ/4 to between λ/5 and λ/12 are reported here. The input and output lines at the three ports and the lines comprising the divider itself are coplanar waveguide (CPW) and asymmetric coplanar stripline (ACPS), respectively. The 10 GHz power dividers are fabricated on high resistivity silicon (HRS) and alumina wafers. These miniaturized dividers are 74% smaller than conventional Wilkinson power dividers, and have a return loss better than +30 dB and an insertion loss less than 0.55 dB. Design equations and a discussion about the effect of parasitic reactance on the isolation are presented for the first time     

一种基于内匹配器件的功率分配器设计

介绍了一种基于内匹配功率管的Wilkinson微带功率分配器设计新思路。传统Wilkinson微带功率分配器在低频段体积大,用于内匹配功率管时很难在规定的尺寸范围内使用,采用高介电常数陶瓷基片辐射损耗大,直流转换效率低。适当引入不连续性,提高端口阻抗值,端口阻抗引入的虚部参与后续匹配网络的新型Wilkinson微带功率分配器,与传统Wilkinson功率分配器相比,体积更小,效率更高,有很好的实用价值。设计的工作频段在5.2～5.8 GHz的Wilkinson微带功率分配器,在整个频带内输出功率大于50 dBm,饱和功率增益高于7 dB,功率附加效率大于30%。     

A Parallel-Strip Ring Power Divider With High Isolation and Arbitrary Power-Dividing Ratio

In this paper, a new power divider concept, which provides high flexibility of transmission line characteristic impedance and port impedance, is proposed. This power divider is implemented on a parallel-strip line, which is a balanced transmission line. By implementing the advantages and uniqueness of the parallel-strip line, the divider outperforms the conventional divider in terms of isolation bandwidths. A swap structure of the two lines of the parallel-strip line is employed in this design, which is critical for the isolation enhancements. A lumped-circuit model of the parallel-strip swap including all parasitic effects has been analyzed. An equal power divider with center frequency of 2 GHz was designed to demonstrate the idea. The experimental results show that the equal power divider has 96.5% -10-dB impedance bandwidth with more than 25-dB isolation and less than 0.7-dB insertion loss. In order to generalize the concept with an arbitrary power ratio, we also realize unequal power dividers with the same isolation characteristics. The impedance bandwidth of the proposed power divider will increase with the dividing ratio, which is opposite to the conventional Wilkinson power divider. Unequal dividers with dividing ratios of 1 : 2 and 1 : 12 are designed and measured. Additionally, a frequency independent 180 power divider has been realized with less than 2 phase errors.     

WiIkinson功分器改进和研究

随着通信技术的加速发展,传统的Wilkinson功分器已经无法满足多频及宽带的技术需求。基于ADS仿真设计软件,根据传统的功分器原理和结构,设计了一款谐振频率在900MHz附近的标准Wilkinson功分器。考虑到目前的实际需求,对其结构进行了适当调整和改进,从而仿真设计出了频率在900MHz附近的宽带Wilkinson功分器以及谐振频率为900MHz和2．OGHz的双频Wilkinson功分器,并且对其进行了良率分析,最终的仿真结果实现了预期的传输特性。     

Synthesis of Broad-Band 3-dB Hybrids Based on the 2-Way Power Divider

The synthesis of broad-band 2-way Wilkinson hybrids is well known. The even- and odd-mode analysis results in two equivalent circuits where the synthesis of the odd mode is done by computer optimization. This paper shows an exact synthesis of 2-way Wilkinson power dividers having one isolation resistor, but an arbitrary number of quarter-wave transformers. A large number of circuits have been synthesized with up to 6 quarter-wave transformers. The 2-way Wilkinson hybrid can be extended to a 4-port component. This 4-port component can operate as a 180° or 90° 3-dB hybrid depending on the input port. The hybrid has a high directivity independent of frequency when used as a 180° hybrid. Experimental results are given for a 2-way divider and a 3-dB hybrid built in microstrip with a center frequency of 5 GHz.     

Coupled line power divider with compact size and bandpass response

The design and implementation of a new power divider using coupled microstrip lines are presented. The proposed divider can be considered as an integration of a single-stage coupled line bandpass filter and a conventional Wilkinson divider. The area of the divider layout is compact owing to the small width and spacing of the coupled lines. Two-way and three-way equal power dividers are designed for the bandwidth between 3-5 GHz having a measured power division of -3.2 and -5 dB, respectively.     

Optimization Design of Muti-Band Wilkinson Power Divider by the Method of Genetic Algorithm

Design of multi-band Wilkinson power dividers using genetic algorithm are proposed. Based on the ideal transmission line model and the concept of the even-odd modes analysis, the design equations of the multi-band equal-power split WPD with the multi-section transmission line and their corresponding isolation resistances are given. The optimal solutions are obtained via the process of the genetic algorithm optimization. Some numerical examples of the dual-band, tri-band and quad-band Wilkinson power divider are presented to verify the proposed design method.     

Miniature Four-Way and Two-Way 24 GHz Wilkinson Power Dividers in 0.13 μm CMOS

This letter presents 24 GHz four-way and two-way miniature Wilkinson power dividers (PDs) in a standard CMOS technology. The chip area is significantly reduced using a lumped-element design, and the effective areas of four-way and two-way Wilkinson dividers are 0.33 times 0.33 mm² and 0.12 times 0.29 mm², respectively. The four-way Wilkinson divider results in an insertion loss <2.4 dB, an input/output return loss better 15.5 dB, and a port-to-port isolation >24.7 dB from 22 to 26 GHz. The two-way Wilkinson divider results in an insertion loss <1.4 dB, an input/output return loss better 8.9 dB, and a port-to-port isolation >14.8 dB from 22 to 26 GHz. To the author's knowledge, this is the first demonstration of 24 GHz four-way Wilkinson PD in a standard CMOS technology.