基于BCH码的NAND Flash纠错算法设计与实现

针对当前NAND Flash存储结构的特性,提出一种纠错能力较强的ECC校验电路结构,设计一种高效并行的BCH编译码器的电路,在关键方程计算过程中采用了无求逆的BM算法,避免了迭代过程中的有限域求逆运算.通过流水线技术与乒乓操作技术,实现 以较小的硬件资源开销提高纠错电路的数据吞吐性能.该ECC纠错电路在Xilinx Vivado上进行仿真,并测试分析.通过测试可以发现,在相同的系统时钟频率下,该ECC纠错电路的数据吞吐率是典型串行纠错电路的8倍,并且通过两级流水线的译码方式,使得译码速度得到大幅度提升,很好地提高了译码效率,同时纠错能力能够满足当前NAND Flash技术的要求;与传统的 NAND flash 纠错电路相比,该纠错电路结构可移植性强,并且灵活性较强,通过调整BCH码的校验位数目,即可满足不同的纠错要求.     

A Quantitative Study of Endurance Characteristics and Its Temperature Dependance of Embedded Flash Memories With 2T-FNFN nor Device Architecture

A quantitative study on the endurance of an embedded Flash memory with 2T-FNFN device architecture in a 0.13-mum technology node has been presented in this paper. Physical insights of 2T-FNFN device degradation have been obtained through stressing and characterizing large parallel arrays of flash transistors (with floating gate connected). Experiments are carried out on large random accessible arrays based on the 2T-FNFN cells, at a wide temperature range and with different program/erase (P/E) voltages. An empirical model has been developed to describe the temperature-dependent degradation of the program window. This model fits the experimental data over the whole temperature range, and the endurance performance with single-shot P/E cycles exceeds 1 million cycles. This paper provides a method for flash endurance characterization and modeling.     

Fast and sensitive electret polymer characterization by extended floating gate MOSFET

A new characterization method for charge conditions in electret polymer films is proposed. This method uses the change of the threshold voltage in an EEPROM (electrically erasable and programmable read-only memory) device to evaluate the effective charge density in electret. The EEPROM device has an extended floating gate that is capacitively coupled to a sensing gate in direct contact with the electret polymer film. It also has a control gate similar to that in the conventional EEPROM device driven by test signals. By the total capacitive loads and effective charges seen on the floating gate, the surface potential of the transistor channel in the subthreshold region is a linear function of effective electret charge density. Representative measurements with several electret charging conditions, such as photo poling and mechano poling are provided. With the bandwidth of the EEPROM device typically much higher than 1 kHz, real-time charging characteristics with sub-millisecond resolution can be obtained.     

Future directions and challenges for ETox flash memory scaling

The physical and electrical scaling challenges for ETox/spl trade/ Flash memory, including reliability considerations, will be reviewed with potential directions for solutions identified. As Flash scales into the sub-100-nm regime, challenges arise due to the high voltage/field requirement of the programming and erase mechanisms and the stringent charge storage requirement of the dielectrics. These challenges will be overcome with innovations in new materials, new cell structures, and memory error management. Using these techniques will extend the viability of Flash memory to at least the 45-nm generation.     

Hybrid numerical analysis of a high-speed non-volatile suspended gate silicon nanodot memory (SGSNM)

We present a hybrid numerical analysis of a high-speed and non-volatile suspended gate silicon nanodot memory (SGSNM) which co-integrates a nano-electromechanical (NEM) control gate with a MOSFET as a readout element and silicon nanodots as a floating gate. A hybrid NEM-MOS circuit simulation is developed by taking account of the pull-in/pull-out operation of the suspended gate and electron tunnelling processes through the tunnel oxide layer as behavioural models. The signals for programming, erasing and reading are successfully achieved at circuit level simulation. The programming and erasing times are found as short as 2.5 nsec for a SGSNM with a 1-μm-long suspended gate, which is a summation of the mechanical pull-in/pull-out times and the tunnel charging/discharging times.     

Reliability Analysis of Memories Suffering Multiple Bit Upsets

The reliability of memory systems that are exposed to soft errors has been studied in the past with the aim of deriving the mean time to failure (MTTF) and the probability of failing in a given time interval. On those studies, the soft errors were considered to arrive following a Poissonian basis and they were assumed to be single uncorrelated events (each event causes only one soft error). Recent studies suggest that multiple bit upsets (MBUs) are a significant part of the error events in advanced memory technologies and that they will continue to grow in the next technology nodes. The errors in an MBU are normally caused by the same physical event and therefore affect memory cells that are close together. This poses a major problem to memories that are protected with per-word single error correction codes, as an MBU is likely to affect two or more bits in the same word, causing an uncorrectable error. To avoid that problem, interleaving is used to ensure that cells that are physically close together belong to different logical words, so that the errors in an MBU are distributed over a number of words each suffering only one error. Although some works have been done that characterize memories under radiation tests, no mathematical model of the effect of MBUs on the reliability of a memory has been proposed in the literature, to the best of the authors' knowledge. Therefore, in this paper, the reliability of memories suffering MBUs is analyzed in detail. The fundamental result from that analysis is that the MTTF of a memory exposed to MBUs can be approximated using the existing results for single event upsets by adjusting the error arrival rate.     

Operation Simulation of an 8F21T2C-Type Ferroelectric Memory Array with a Revised Data Writing Method

A planar 1T2C-type ferroelectric memory cell structure which has a unit cell area of 8F² (F: minimum feature length) has been proposed. In this structure, the gate area, which is covered with a floating gate electrode, is 3F in length and F in width. Through the SPICE simulation for a 2 × 2 cell array, the basic operation for 8F² 1T2C-type memory cell was identified. Also, data disturbance problem during the data writing process in the 1T2C-type ferroelectric memory array was investigated using an equivalent capacitor model. Based on the analysis, a modified V/3 rule voltage application method for reducing the data disturbance effect was proposed and its validity was verified by SPICE simulation.     

Radiation-induced soft errors in advanced semiconductor technologies

The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.     

基于随差遗忘长短期记忆的风电功率实时预测

由于标准长短期记忆(long short-term memory,LSTM)遗忘门更新方式不能实时反映预测误差对模型预测的修正作用,提出随差遗忘长短期记忆(Error Following Forget Gate-based LSTM,EFFG-based LSTM)的风电功率实时预测模型.用上一时刻的风电功率预测值与实...     

Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation

Scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) to below a few tens of nanometer has failed to make significant improvements. FinFETs were introduced to replace MOS devices in circuits, offering good performance improvement in the nanoscale regime. Memories occupy a major portion of chip area. Their reliability is a primary concern in harsh environments such as cosmic radiation. Also, in the nanoscale regime, reliability proves to be challenging. We present herein FinFET- and junctionless FinFET-based 6T-static random-access memories (SRAMs) for the 16-nm technology node. In the literature so far, either drain or gate strike has been considered. In this work, we studied irradiation in both the drain and the gate region. The FinFET-based 6T-SRAM showed higher hardness to single-event upset (SEU) radiation in both regions compared to junctionless FinFET-based 6T-SRAM.     

A review of ionizing radiation effects in floating gate memories

The effects of ionizing radiation on microelectronics are traditionally a concern for devices intended for the space use, but they are becoming important even at ground level. Ionizing radiation effects can be broadly divided in two classes: total ionizing dose (progressive buildup of defects) and single event effects (macroscopic result of a single microscopic event). In both cases, ionizing radiation can lead to severe degradation of device performance, possibly resulting in device failure. This work is a review of literature results concerning both classes of ionizing radiation-related phenomena on floating gate memories. Regardless of its nature, ionizing radiation impacts two aspects of the performance and reliability of floating gate memories: the functionality and the adherence to specifications of the control circuitry, and the degradation of stored information in the array itself.     

Sensing margin trend with technology scaling in MRAM

Magnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano‐meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation. Copyright © 2010 John Wiley & Sons, Ltd.     

TMS320VC5509A并行Flash的二次自举方法研究

TMS320VC5509A的Boot Loader不支持翻页访问外部存储器的功能,无法实现大于16KB的程序自举。为解决这一问题,提出基于VC5509A并行Flash的二次自举方法。采用容量为1MB的Nor Flash芯片S29AL008D作为存储DSP程序的外部存储空间,利用FPGA芯片控制Flash的高位地址线,实现DSP对Flash的翻页访问。介绍了VC5509A的Boot Loader工作原理,提出编写Second Loader程序实现DSP的二次自举。该方法所采用的硬件架构具有普遍适用性,二次自举方法简单实用,使得VC5509A能够支持大于16KB程序的自举。     

低复杂度高阶 APSK 解映射方法与实现结构

针对高阶幅度相移键控(amplitude phase shift keying, APSK)解映射复杂度,不易硬件实现的问题,提出了一种低复杂度的APSK解映射方案及电路实现结构。具体而言,基于Max-Log-MAP算法,分析APSK星座图对称性并进行区域划分,对落到每个区域的接收符号比特软信息计算进行化简,得到具有低计算量的解映射公式。进一步,利用简化后每个比特软信息计算公式的特点,设计了软信息计算电路结构并在现场可编程门阵列(field programmable gate array, FPGA)硬件平台上进行了性能测试。测试结果表明,信噪比为14 dB时,利用简化方法实现的APSK解映射电路可实现10~(-5)的误比特率(bit error rate,BER),与传统解映射算法性能接近,且具有较低的硬件资源消耗。     

TrueFFS原理及其在Flash存储器上的应用

作为嵌入式领域应用最为广泛的存储设备，Flash存储器具有高密度和良好的存取速度等优点。介绍了专为Flash存储器提供统一接口的TrueFFS的结构和工作原理，并给出了在NOR Flash上的具体实现过程。通过结合VxWorks的dosFS文件系统，实现了对Flash存储器的实时读写。     

One-sided 10T static-random access memory cell for energy-efficient and noise-immune internet of things applications

This paper presents a one-sided 10-transistors static-random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy-efficient SRAM cells are necessary to raise the battery lifetime. The bit-cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate-wrap-around (GWA) carbon nanotube (CNT)-gate-diffusion input (GDI) technique and only one-bit line to perform both read and write operations to minimize active power consumption. The proposed bit-cell uses a transmission gate network and write-assist schemes to significantly improve the write-ability and stack read-decoupling technique to enhance hold-/read-stability. Moreover, a memory mini-array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write- and read-yield parameters for the proposed SRAM bit-cell are about 22% and 13% better than counterpart bit-cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit-cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit-cell in the real-world application, a memory array architecture with an online (or off-chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy-efficient and noise-immunity IoT platforms.     

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.     

Mobile ion-induced data retention failure in NOR flash memory cell

Data retention failures due to nonoptimized processes in NOR-type flash memory cells are presented. Contrary to the charge leakage through defective oxide dielectric surrounding the floating gate, the data loss observed depends on whether the bit line contact is close to the cell or not. It is found that the data loss exhibits a charge-state dependence during baking stresses as well as temperature dependence. Based on experimental results, sodium movement in sidewall spacers is established as an origin for the data retention failure in NOR-type flash memory cells. Employing a thin nitride overlayer results in a good data retention, supporting the hypothesis of sodium movement     

电力系统测控仪表中数据存储方案设计

对于故障数据、重要的实时数据以及配置参数等关键数据,常规的保存方法是利用EEPROM,SRAM＋电池或者NVRAM等。MSP430F149单片杌内部有60kB的F1ash模块,该模块可以在应用中执行写操作;铁电存储器（FRAM）有读写无延时、擦写次数多等优点,利用MSP430F149单片机内Hash模块和FRAM存储器的特点,采用缓冲思想,设计了一种应用于电力参数监测仪表中的数据存储方案,并应用到了实际开发的产品中,取得了较好的效果。     

Flash memory: towards single-electronics

Since their invention in 1984, flash memories have evolved from single device components to megabit nonvolatile memory (NVM) arrays. Flash memories were born from the need to find easily scalable replacements for EPROMs (erasable programmable read only memory) and EEPROMs (electrically erasable programmable read only memory). Unlike EPROMs and EEPROMs, flash memory cells provide single-cell electrical program and fast simultaneous block electrical erase. Thus, a small cell size is combined with a fast in-system erase capability.