Large-scale photonic integrated circuits

100-Gb/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb/s on a DWDM wavelength grid. Optical system performance results across a representative DWDM long-haul link are presented for a next-generation optical transport system using these large-scale PICs. The large-scale PIC enables significant reductions in cost, packaging complexity, size, fiber coupling, and power consumption.     

Thermal issues in next-generation integrated circuits

The drive for higher performance has led to greater integration and higher clock frequency of microprocessor chips. This translates into higher heat dissipation and, therefore, effective cooling of electronic chips is becoming increasingly important for their reliable performance. We systematically explore the limits for heat removal from a model chip in various configurations. First, the heat removal from a bare chip by pure heat conduction and convection is studied to establish the theoretical limit of heat removal from a bare die bound by an infinite medium. This is followed by an analysis of heat removal from a packaged chip by evaluating the thermal resistance due to individual packaging elements. The analysis results allow us to identify the bottlenecks in the thermal performance of current generation packages, and to motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.     

Optoelectronic-VLSI: photonics integrated with VLSI circuits

Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity complementary metal-oxide-semiconductor logic technologies     

Photonic integrated circuits fabricated using ion implantation

Intermixing the wells and barriers of quantum-well (QW) laser heterostructures generally results in an increase in the bandgap energy and is accompanied by changes in the refractive index. A technique, based on ion implantation-induced QW intermixing, has been developed to enhance the quantum-well intermixing (QWI) rate in selected areas of a wafer. Such processes offer the prospect of a powerful and simple fabrication route for the integration of discrete optoelectronic devices and for forming photonic integrated circuits     

用于大规模集成电路的多级布局规划设计

本文提出了一种适用于处理大规模集成电路设计的布图规划问题的V型多级不可分割固定边框布图规划算法。该算法以追求电路设计在短耗时前提下的最短布线为目的,同时满足电路原本的面积边框限制。通过计算机仿真,实验结果体现了所提出多级布局规划算法的有效性。     

Hybrid integration of VCSEL's to CMOS integrated circuits

Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4×4 and/or 8×8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 Ω were measured, indicating good electrical contact was obtained. Optical power as high as ~10 mW for a VCSEL with a 20-μm aperture and 0.7 mW with a 6-μm aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS     

A quantum-well-intermixing process for wavelength-agile photonic integrated circuits

Wavelength-agile photonic integrated circuits are fabricated using a one-step ion implantation quantum-well intermixing process. In this paper, we discuss, the issues in processing optimized widely tunable multisection lasers using this technique and present the results achieved using this process. This quantum-well intermixing process is general in its application and can be used to monolithically integrate a wide variety of optoelectronic components with widely tunable lasers.     

Circuit-level modeling of soft errors in integrated circuits

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.     

Time‐mode circuits for analog computation

We introduce time‐mode circuits, a set of basic circuit building blocks for analog computation using a temporal step function representation for the inputs and outputs. These novel time‐mode circuits are low power, provide good noise performance and offer improved dynamic range. The design, IC implementation and detailed theoretical signal‐to‐noise ratio (SNR) analysis of a prototype time‐mode circuit—a weighted average computation circuit—are discussed. This new way of computation is studied with respect to existing conventional voltage‐mode and current‐mode circuits. Two possible applications of these time‐mode circuits are presented: an edge detection circuit for 16 pixels and a 3‐tap FIR filter that provides an SNR of 64 dB. Copyright © 2008 John Wiley & Sons, Ltd.     

Analysis and simulation of substrate coupling in integrated circuits

A technique is presented which allows efficient calculation of substrate-coupling macromodels in integrated circuits. the technique can be used to calculate node-to-node resistances or impedances in substrate models. Examples of the technique applied to several test structures are presented.     

Optimization of large change tolerances of linear integrated circuits

Optimization of element tolerances is a very important but also time consuming part of integrated circuit design. In this paper an algorithm is presented for the worst case optimal assignment of large change tolerances, in which a significant simplification of the problem is obtained for a class of linear circuits. This is due to taking advantage of the bilinear dependence of the network functions on element values and to some simplifications assumed. The minimal cost of the circuit is the objective function.     

数字电路封装的串扰测试方法研究

梳理了数字电路封装串扰测试方法的发展历史,总结了串扰的影响因素。基于对业界串扰测试方法的分析,比较了各种方法间的区别和优缺点,分析了美军标MIL-STD-883K中串扰测试方法很少修订却长期存在的原因。明确了美军标及其他串扰测试方法的适用范围,提出了我国相应标准制修订方向的建议。测试结果表明,标准中的现有方法在评估串扰对整体电路影响方面手段有欠缺,需要结合电磁仿真对串扰影响做出整体评估,并利用实际测试对仿真结果进行校准,从而提高模拟的准确度,此方法可以在我国相应标准的制修订中加以采用。     

Explosive growth calls for more mixed-voltage analog integrated circuits

The explosive growth of the consumer electronics market in the last two decades has led to a great demand of low-cost, high-performance integrated systems. The most effective way for cost minimization is by manufacturing the system chips in advanced nanoscale complementary metal oxide semiconductor (CMOS) technologies, given that most modern microsystems are dominated by digital circuits. Entered into the nanoscale CMOS regime, 90-, 65- or 45-nm processes are expected to deliver substantial improvements in speed and power reduction for digital circuits in comparison to the current sub-micron-scale technologies.     

High-sensitivity cytometric detection using fluidic-photonic integrated circuits with array waveguides

We demonstrate a new detection scheme for a microfabricated flow cytometer. The fluidic-photonic integrated circuits (FPICs) that perform flow cytometric detection possess new functionality, such as on-chip excitation, time-of-flight measurement, and above all, greatly enhanced fluorescence detection sensitivity. Using the architecture of space-division waveguide demultiplexer and the technique of cross-correlation analysis, we obtained high detection sensitivity with a simple light source and a detector, without high-power laser excitation and lock-in amplifier (or photomultiplier tube) detection. Besides improving cytometric detection, the technology of integrating microfluidic circuits with photonic circuits into the FPIC presents a new platform for sophisticated biomedical-sensing devices with significant cost, size, and performance advantages.     

Method of moments modelling of cylindrical microwave integrated circuits interconnections

In this paper, a numerical technique suitable for characterizing a wide variety of interconnection configurations printed on cylindrical surfaces, is presented. The interconnection lines may have either finite or infinitesimal cross‐sections. To model cylindrical interfaces, suitable space‐domain integral equations are formulated to represent the potential on conductors and electric field at dielectric interfaces. The solution of the integral equations is then obtained numerically by applying the method of moments (MOM). The objective of this approach is to determine the capacitance matrix of cylindrical interconnection systems with different configurations. From the capacitance matrix, other quantities such as characteristic impedance, coupling coefficient and effective permittivity can be determined. The numerical technique described in this paper is implemented as a general computer program. Various circular cylindrical as well as elliptical cylindrical structures have been solved including microstrip lines and coplanar waveguide lines. The results obtained compare very well with other published data. Copyright © 2004 John Wiley & Sons, Ltd.     

三毫米单片集成电路噪声系数测量技术

采用双平衡混频器和本振信号源,把3 mm频段的噪声信号下变频至噪声系数分析仪的频率范围内,配探针台作在片噪声系数测量。为了减小本振源相位噪声和系统元件损耗的影响,在混频器前加低噪声放大器,使系统更加稳定,重复性好、准确度高。该系统具有频率范围宽可扩展至75～110 GHz、结构简单、成本低的特点。     

Novel integrated photodetector on Si LSI circuits. Opticallycontrolled MOSFET

We have demonstrated a novel integrated photo-detector on Si large-scale integration circuits. This device integrated the light absorption region on the gate of metal-oxide-semiconductor field-effect transistor (MOSFET), and the long wavelength light controls the current of MOSFET. The GaInAs-InP multiple-quantum-well absorption region and SiO₂ of the MOSFET were directly bonded. From the experimental results, we confirmed that the light-controlled current was increased by shortening the gate length of the MOSFET, and that an 1850 A/W responsivity was obtained in a 3.5-μm gate length device using an irradiation of 1.5-μm wavelength light