6H-SiC p+-n junctions fabricated by berylliumimplantation

The use of beryllium (Be) as an alternate p-type dopant for implanted silicon carbide (SiC) p⁺-n junctions is experimentally demonstrated. The implanted layers have been characterized with photoluminescence (PL) as well as secondary ion mass spectrometry (SIMS) measurements. In comparison with boron implanted p ⁺-n junctions, Be-implanted junctions show improvement in the forward characteristics while exhibiting slightly higher reverse leakages. The activation energies extracted from the forward conduction and reverse leakage characteristics of the Be-diodes are 1.5 eV, and 0.13 eV, respectively. Moreover, activation energy extraction in the forward ohmic region reveals the Be impurity level at 0.38±0.04 eV. The minority carrier lifetime extracted from reverse recovery measurements is as high as 160 ns for the Be-diodes compared to 82 ns obtained for the B-diodes     

Damage removal/dopant diffusion tradeoffs in ultra-shallowimplanted p+-n junctions

The tradeoffs between implant damage annealing and shallow junction formation are investigated. For very-low-energy amorphizing implants the time for damage anneal has a fourth-power dependence on depth below the Si surface. The depth effect depends on the type of amorphizing ion. It is shown that as a result, implanted B in Ge-preamorphized Si diffuses with no detectable self-interstitial supersaturation if the damage is <600 Å deep. Conditions for forming defect-free, shallow p⁺-n junctions are described in design curves and comparisons are made between several junction-formation approaches. Implantation of B at energies below 2 keV offers an attractive way of achieving 500-Å junctions     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

p^＋—n^——n结的势垒分布

GaP:N绿色LED发光效率的提高有赖于对其结构参数的优化。根据载流子分布的连续性,由泊松方程自治求解,得出了半导体n^--n结势垒分布的计算方法。在此基础上,计入n^-区内的电位降,计算了商用光二极管p^ -n^--n结构的势垒分布,为整体结构的参数优化准备了必要的条件。     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

Simultaneous formation of silicide ohmic contacts and shallow p+-n junctions by ion-beam mixing and rapid thermal annealing

Low-resistivity, uniform molybdenum silicide layers, and shallow p⁺-n junctions with good electrical characteristics have been formed using ion-beam mixing and rapid thermal annealing (RTA). Detailed reverse leakage current data on RTA annealed diodes, which were formed by implanting BF2⁺into Si substrates through the molybdenum films deposited on Si, are presented. The process has a great potential for CMOS fabrication with self-aligned silicided source, drain, and gate.     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

Low-temperature fabrication of p+-n diodes with300-Å junction depth

Gas immersion laser doping (GILD) was used to fabricate p⁺ -n diodes with 300-Å junction depth. These diodes exhibit ideality factors of 1.01-1.05 over seven decades of current, reverse leakage current densities ⩽10 nA/cm² at -5-V reverse bias, breakdown voltages above 100 V, and electrical activation of the boron impurity to concentrations approaching 1×10²¹ atoms/cm³. This behavior is achieved without the use of a furnace or rapid thermal anneal     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

The spatial variation of the quasi-Fermi potentials in reverse-biased p+-n junctions and its implications in transition region capacitance calculations

The spatial variation of the quasi-Fermi potentials in asymmetrical step p⁺-n junctions under reverse bias conditions is analyzed following an approximate procedure already described in the literature for the symmetrical junctions. The results obtained in this analysis are used to check the validity of the quasi-equilibrium approximation in capacitance calculations.     

Evaluation of the profile constants of p+-n-n+hyperabrupt junctions

A method for evaluating the profile constants of a p⁺-n-n⁺hyperabrupt junction is given. The method is useful in the design and characterization of hyperabrupt tuning varactors.     

Thin-film SOI CMOS transistors with p+-polysilicon gates

A comparison is given of the use of p⁺-polysilicon and n⁺-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide     

Low-temperature growth of silicon-boron layer as solid diffusionsource for polysilicon contacted p+-n shallow junction

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p⁺-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF₂⁺-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF₂⁺ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 Å, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm² at -5 V were obtained. As the junction depth shrank to 300 Å, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm², respectively. These results demonstrated that a uniform ultrashallow p⁺-n junction can be obtained by using a thin Si-B layer as a diffusion source     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

p+-n junction formed by dual implantation of Zn and As in GaAs junction field-effect transistors

The performance of a p+-n junction formed in GaAs by dual implantation of Zn and As was investigated. The transconductance in linear operation of the junction field-effect transistors (JFET's) in which the p+-gate was formed by the dual implantation was measured and analyzed on a simple one-dimensional model. As the dose of As was increased, the devices showed negatively shifted pinchoff voltage and higher transconductance. It was found that the co-implantation of As significantly decreased the width of the compensated layer in the junction, which improved the JFET's performance.     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²