A simple model for the overlap capacitance of a VLSI MOS device

A simple approximate analytical expression for the overlap capacitance between gate- and source-drain of a VLSI MOS device is derived. The expression takes into account finite polysilicon gate thickness, source-drain junction depth and different dielectric constants of silicon and oxide. A numerical procedure is also described to calculate the exact overlap capacitance with fringing, using the solution of Laplace's equation. A comparison is made to check the accuracy of the analytical expression. Good agreement is found. Experimently obtained gate-source capacitance curves are described. Overlap capacitance and fringing component values derived from these curves are also in good agreement to those predicted by the model.     

A new method to extract EOT of ultrathin gate dielectric with high leakage current

The standard capacitance-voltage (C-V ) technique can no longer determine accurately the equivalent oxide thickness (EOT) for an advanced CMOS transistor with ultrathin gate dielectric where there is high gate leakage current, as well as series resistance; this situation will get worse as the CMOS transistor's scaling trend continues. This paper describes a simple methodology based on dual-frequency C-V measurement and four-element circuit model to extract accurately the EOT in the presence of gate leakage current and series resistance. This method can be effective with a current density of 1000 A/cm/sup 2/ for a 10 /spl mu/m /spl times/10 /spl mu/m capacitor. Such a high current density will satisfy the projected gate leakage current requirements for many generations of CMOS technologies, as specified in the 2003 International Technology Roadmap for Semiconductors.     

A new charge conserving capacitance model for GaAs MESFET's

We present a new charge conserving capacitance model for Gallium-Arsenide (GaAs) metal semiconductor field effect transistors (MESFET's) based on the quasi-static approximation and a proper partitioning of the channel charge between the source and the drain terminals. A total of nine so-called transcapacitances were determined by taking derivatives of the various terminal charges with respect to the voltages at source, drain, and gate. The transcapacitances are nonreciprocal, i.e., C_ij≠C_ji when i≠j, and can be organized in a 3×3 matrix incorporating Kirchhoff's current law (charge conservation) and independence of reference. The present capacitance model is valid both above and below threshold, and shows good agreement with experimental data over a wide range of gate and drain biases. The model is analytical and suitable for implementation in circuit simulators     

A new electron-trapping model for the gate insulator of insulated gate field-effect transistors

In the present paper, a new model for electron trapping kinetics in the gate insulator of an insulated gate field-effect transistor (IGFET) is proposed. This model includes a continuous variation of the trapping cross section, σ_o, as a function of the number of filled traps,N _D . The dependency of σ_o is believed to be related physically to the annihilation, or buildup of coulombic charge, which effect has heretofore been neglected in first-order trapping kinetics that describe the entire defect concentration range. The result is that in order to model the experimental data fewer classes of trap cross sections are needed. AsN _D traps fill, the trapping cross section, σ_o, is assumed to be reduced by a factor (1 -N _D /N _T ) whereN _T is the total number of available traps per unit area. This decrease in δ_o is consistent, physically, with a concept of increasing repulsion of carriers as traps fill. This new model also indicates that the number of injected electrons needed to populate 99% of the total traps is about 20 times greater than that predicted by the existing first-order trapping kinetics model. Comparisons between the results of the new model and the first-order trapping kinetics model applied to experimental defect data are also given.     

Increase of gate capacitance in DMOST

The gate capacitance of an n-channel DMOST at nonzero drain current biasing exceeds that of a similar conventional MOST and may even exceed the gate oxide capacitance. This effect is due to the behavior of mobile electrons in the device. The fundamental operation of the DMOST is understood through the use of a two-dimensional computer analysis. Based on this insight, the increase of the gate capacitance is clarified in terms of the electron velocity between the source and the drain. Gate capacitance measurements are carried out on experimental DMOST's, which are made on a p^-background as well as on an n^-epitaxial layer. The measuredC-Vcurves qualitatively confirm the theory on the increase of the gate capacitance in its dependence on the background of the DMOST and the applied dc voltages.     

A new insulated gate tetrode with high drain breakdown potential and low miller feedback capacitance

Insulated gate field effect transistors (IGFET's) with the gate offset from the drain electrode exhibit high drain breakdown potential and very low Miller feedback capacitance. The new insulated gate tetrode (IGT) described in this paper utilizes a second stacked gate to create the offset channel. The main advantage is the possibility of optimizing the device performance, especially the drain breakdown potential for bothP-andN-channel devices. Considered in the paper are design and fabrication problems,V-Icharacteristics, drain breakdown potential, dynamic drain resistance, small-signal equivalent circuit, and large-signal limitations.P-channel IGT's with drain breakdown potentials up to 300 V have been built. The design of the IGT depends mainly on the tradeoff between drain breakdown potential and the limited frequency response caused by the time constant of the offset channel. The results to date indicate that the IGT has a large drain voltage range and an extremely low Miller feedback capacitance and is adaptable to different operating conditions. The IGT appears very promising for use in power amplifiers and switching applications.     

A new method to extract gate coupling ratio and oxide trapped charge in flash memory cell

A new method to obtain the gate coupling ratio (α_g) and oxide trapped charge (Q_ox) as a result of cycling in flash memory cells is described here. Three cells with an equivalent physical structure but different erase characteristics are measured. The threshold changes versus erase times are fitted to the charge removal rate calculated based on Fowler-Nordheim (FN) tunneling and the capacitive relations among all nodes. The extracted α_g is independent of technologies and this method is particular useful when the profile of the floating gate is not traditionally rectangular owing to advanced processes such as trapezoidal poly etch or a poly-spacer addition on the floating gate sidewall. The Q_ox can also be determined once α_g is extracted.     

Small-signal gate-to-drain capacitance of MOSFET as a diagnostic tool for hot-carrier induced degradation

In this paper a method for the study of hot-carrier induced charge centers in MOSFETs based on a small-signal gate-to-drain capacitance measurement is described. Numerical modeling and simulation is used to provide an understanding of the effects of spatially localized trapped carriers and interface states on this capacitance. Experimental gate-to-drain capacitance results are presented and compared with charge pumping measurements. This method is used to investigate hot-carrier degradation of n- and p-channel MOSFETs after drain avalanche hot-carrier stress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface states in the top half of the silicon bandgap.     

A PEEC with a new capacitance model for circuit simulation ofinterconnects and packaging structures

In this paper, a modified partial-element equivalent-circuit (PEEC) model, i.e., (L_p, A&oarr;, R, ϵf)PEEC, is introduced. In such a model, no equivalent circuit, but a set of state equations for the variables representing the function of circuit, are given to model a three-dimensional structure. Unlike the original (L_p, P, R, ϵf) PEEC model, the definition of vector potential A&oarr; with integral form and the Lorentz gauge are used in expanding the basic integral equation instead of the definition of the scalar potential φ with integral form. This can directly lead to the state equations, and the capacitance extraction can be replaced by the calculation of the divergence of A&oarr;, which is analytical. For analysis of most interconnect and packaging problems, generally containing complex dielectric structures, the new model can save a large part of computing time. The validity of the new model is verified by the analysis in time and frequency domain with several examples of typical interconnect and packaging structures, and the results with this new method agree well with those of other papers     

CASFET: A MOSFET-JFET cascode device with ultralow gate capacitance

A field-effect transistor is described that combines a short-gate MOSFET with a long-channel JFET in a cascode configuration. The composite device, a CASFET, can have a very low input capacitance due to the short gate of the MOSFET combined with the reduced Miller capacitance of the cascode. The long channel of the JFET insures that the CASFET has high output resistance. This paper discusses CASFET fabrication, performance, and modeling.     

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator (DCO) using a three-transistor XOR gate as the variable load has been presented. A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-, five- and seven-stage DCO circuits have been designed using the proposed delay cell. The output frequency is controlled digitally with bits applied to the delay cells. The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW, respectively, with a change in the control word 111-000. The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW, respectively, with a change in the control word 11111-00000. Moreover, the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW, respectively, with a varying control word 1111111-0000000. The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.     

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator(DCO) using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.     

A methodology to extract the channel current of permeable gate oxide MOSFETs

A methodology to extract the channel current of MOS transistors in the presence of high gate leakage current is presented. The methodology is based on the partitioning of the gate current among the source and drain terminals and it is well suited for devices featuring ultrathin gate oxide and long channels, as those typically employed for mobility measurements. The proposed procedure is compared with the existing method based on a 50%-50% source/drain partition of the gate current, and the dependence of the extraction error associated with these two methods on channel length and bias conditions is studied in detail. It is found that the extraction error is weakly dependent on gate-source and drain-source voltages.     

Modeling for reduced gate capacitance of nanoscale MOSFETs

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate region on gate capacitance. Comparing the theoretical curves with an extensive set of simulation ones has validated this model.     

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET

A simple analytical model for deriving the front and the back gate threshold voltages of a short-channel fully-depleted SOI MOSFET is presented. Taking into account the lateral variations of the front and the back surface potentials, we obtain two-dimensional potential distributions in the fully depleted silicon body, the front oxide layer, and the back oxide layer. From the obtained two- dimensional potential in the silicon body, the minimum values of both front and back surface potentials are derived and used to describe both front and back gate threshold voltages as closed-form expressions in terms of various device geometry parameters and applied bias voltages. Obtained results are found to be in good agreement with the numerically simulated results.     

Charging effect of Si nanocrystals in gate oxide near gate on MOS capacitance

MOS structure with Si nanocrystals embedded in the gate oxide close to the gate has a much larger capacitance compared to a similar MOS structure without the nanocrystals. However, charge trapping in the nanocrystals reduces the capacitance dramatically, and after most of the nanocrystals are charged up the capacitance is much smaller than that of the MOS structure without nanocrystals. An equivalent-capacitance model is proposed to explain the phenomena observed.     

A capacitance model for GaAs MESFETs

A capacitance model for a GaAs MESFET suitable for implementation in the circuit analysis program SPICE is presented. The model consists of nonlinear capacitances that are a function of two voltages. Such a model gives rise to ordinary nonlinear capacitances and transcapacitances. The placement of these elements in the Y matrix is shown. The empirical equations for the gate charge of a GaAs MESFET given provide an accurate SPICE model for the gate charge and capacitances of a MESFET. A comparison of measured capacitance values with the modeled values gives close enough agreement for circuit simulation purposes     

A capacitance model for GaAs MESFET's

We present a new analytical model for small signal capacitances of GaAs MESFET's. This model may be used for epitaxially grown as well as ion-implanted FET's because the effects related to the nonuniform doping profile are included. We also take into account backgating, capping, velocity saturation in the conducting channel, and possible Gunn domain formation in the channel at the drain side of the gate. The model explains complicated voltage dependences of the gate-source and gate-drain capacitances of GaAs microwave FET's and is in fair agreement with the experimental results. This analytical model is quite suitable for the computer-aided design of GaAs microwave FET's and integrated circuits.