Three-dimensional CMOL: three-dimensional integration of CMOS/nanomaterial hybrid digital circuits

The CMOS molecular (CMOL) circuit is a promising hybrid structure incorporating the nanowire crossbar into the CMOS integrated circuit (IC) implementation. In this letter, a novel three-dimensional (3D) architecture of the CMOL circuit is introduced. This structure eliminates the special pin requirement of the original CMOL designs, providing a feasible and efficient solution to build the practical CMOL circuits. In this 3D structure, the density of the nanowire crossbar is doubled. Such a high-density implementation enables the 3D CMOL technology to leap ahead of the IC roadmap by more than three generations.     

Design of a transmission gate based CMOL memory array

A design of a nanoelectronic memory array, compatible with both the molecular switch (nanodevice) electrical characteristics and CMOS 45 nm semiconductor technology node is presented. The proposed transmission gate based CMOL (hybrid CMOS/MOLecular) memory cell does not suffer from the operational difficulties faced by the conventional CMOL cell. The control circuitry with improved multiplexer designs is introduced, and it shows that the required voltage levels to program the nanodevices can be achieved. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cell allowing easier implementation of both logic and memory circuits on the same chip.     

CMOL: Second life for silicon?

This is a brief review of the recent work on the prospective hybrid CMOS/nanowire/nanodevice (“CMOL”) circuits including digital memories, reconfigurable Boolean-logic circuits, and mixed-signal neuromorphic networks. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with the extremely high potential density of molecular-scale two-terminal nanodevices. Relatively large critical dimensions of CMOS components and the “bottom-up” approach to nanodevice fabrication may keep CMOL fabrication costs at affordable level. At the same time, the density of active devices in CMOL circuits may be as high as 10¹² cm² and that they may provide an unparalleled information processing performance, up to 10²⁰ operations per cm² per second, at manageable power consumption.     

Cortical Models Onto CMOL and CMOS— Architectures and Performance/Price

Here we introduce a highly simplified model of the neocortex based on spiking neurons, and then investigate various mappings of this model to the CMOL CrossNet nanogrid nanoarchitecture. The performance/price is estimated for several architectural configurations both with and without nanoscale circuits. In this analysis we explore the time multiplexing of computational hardware for a pulse-based variation of the model. Our analysis demonstrates that the mixed-signal CMOL implementation has the best performance/price in both nonspiking and spiking neural models. However, these circuits also have serious power density issues when interfacing the nanowire crossbars to analog CMOS circuits. Although the results presented here are based on biologically based computation, the use of pulse-based data representation for nanoscale circuits has much potential as a general architectural technique for a range of nanocircuit implementation.     

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.     

基于伪布尔可满足性的纳米CMOS电路单元配置

针对传统布尔可满足性(SAT)法在处理纳米CMOS电路(CMOL)单元配置时,存在合取范式(CNF)表示的约束子句个数过多、中间处理文件过大的问题,该文提出了利用伪布尔可满足性(PBS)来解决CMOL电路的单元配置问题。实验结果显示,相对于传统的SAT法,PBS法在不增加额外的布尔变量集个数的条件下,通过降低编码过程中的约束个数,能有效减少中间处理文件大小,达到提高算法效率和提高处理大电路的能力。     

Efficient Path Delay Test Generation for Custom Designs

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.     

How to automate analog IC designs

Knowledge-based systems that have made the computer-aided design (CAD) of analog circuits feasible are discussed. The three systems-Idac, Oasys, and Opasyn-were formally announced in 1987. Although they differ widely in philosophy, all use common building blocks and produce sized-schematic diagrams showing how transistors, capacitors, and so forth are connected, complete with the components' values-from which custom circuits can be synthesized. These building blocks, however, unlike the ones used in semicustom analog IC design, are not fixed designs from a library. Rather, they can be varied infinitely, according to rules given to the tools by human experts, so that they approach the ideal performance far more closely than is possible with a limited choice of fixed blocks. All told, Idac, Oasys, and Opasyn can automatically synthesize analog circuits from 13 classes of analog building blocks and can produce over 100 distinct circuit topologies. The characteristics of the three systems are discussed and compared     

Statistical Timing Models for Large Macro Cells and IP Blocks Considering Process Variations

Integrated circuits today rely on extensive reuse of IP bocks and macro cells to meet the demand for high performance system-on-chip. We propose a methodology for extracting timing models of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in device and interconnect parameters. Increasing spatial correlations in variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a novel technique for instance-specific calibration of precharacterized timing model. The proposed approach was evaluated on large industrial designs of 1.2- and 3.5-M gates in 65-nm technology and validated against SPICE for accuracy.      

Delay fault testing of IP-based designs via symbolic path modeling

Predesigned blocks called intellectual property (IP) cores are increasingly used for complex system-on-a-chip (SoC) designs. The implementation details of IP cores are often unknown or unavailable, so delay testing of such designs is difficult. We propose a method that can test paths traversing both IP cores and user-defined blocks, an increasingly important but little-studied problem. It models representative paths in IP circuits using an efficient form of binary decision diagram (BDD) and generates test vectors from the BDD model. We also present a partitioning technique, which reduces the BDD size by orders of magnitude and makes the proposed method practical for large designs. Experimental results are presented that show that it robustly tests selected paths without using extra logic and, at the same time, protects the intellectual contents of IP cores     

Measurements on Gallium Arsenide building blocks and implications for analog IC design

Gallium Arsenide technology has offered the promise of very high frequency operation but its potential has not been fully realized due to technological problems which have revealed themselves in undesirable and unpredictable device characteristics. This article presents measured DC characteristics for some current mirrors and transconductors which are believed to be important building blocks for future high-speed GaAs communication circuits. The results presented validate the building block designs within the measurement limitations and show that technology improvements are now producing devices of sufficient quality to allow a sophisticated approach to GaAs circuit designs.     

Wideband precision current sources for integrated circuits

This article introduces two new configurations for precision current sources and current mirrors. Both circuits use n-p-n bipolar devices, but one provides a current source while the other provides a current sink. This permits the use of current sources in IC designs implemented with processes that do not allow p-n-p devices. Analog building blocks such as voltage-to-current converters, active loads, and sink and source current mirrors can be constructed from the new circuits using only n-p-n devices. Furthermore, because these circuits achieve the required precision without the use of high-gain amplifiers, the bandwidths of the circuits are large compared to conventional configurations. The source currents are dependent on a single reference voltage and exhibit good temperature sensitivity.     

Partial evaluation based triple modular redundancy for single event upset mitigation

We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault insertion simulator to evaluate partial redundancy technique on the designs from MCNC′91 benchmark. Experimental results demonstrate that we can reduce the area overhead by up to 39.18% and on average 17.23% of the hardened circuit when compared with the traditional TMR. For circuits with a large number of gates and less number of outputs, there is a significant savings in area. Smaller circuits or circuits with a large number of outputs also show improvement in area savings for increased rounding range.     

BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)

In-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can perform logical operations when subjected to suitable voltages. In this work, a generalized synthesis technique is presented to implement the logic functions inside pure memristive-crossbar. To initiate the process, two novel memristive-designs are proposed for 2:1 multiplexer (MUX) that follow Memristor Aided loGIC (MAGIC) design style. Experimental results showed that each design is at least 68.05 %, 35.92 % more energy-efficient than their existing IMPLY, MAGIC-based designs, respectively. One of our proposed MUX designs is optimized in memristor-count, and the other is latency-optimized. The latency-optimized design offers 20 % improvement in performance compared to its existing IMPLY, MAGIC-based peers. Based on the simulation methodology presented in this work, the memristive-MUXes are simulated in Cadence Virtuoso. Subsequently, our proposed MUX designs are used for the technology mapping of the nodes of the Binary Decision Diagrams (optimized in terms of node, path counts) for the logic functions. Our proposed technique optimizes the implemented logic circuits in terms of memristor-count, step-count, and provides the details for – latency, required memristors, energy, area. Comparison of the synthesis results showed that the circuits generated using our proposed MAGIC-MUXes, are at least 82.21 %, 44 % more energy-efficient, and can offer 18.94 %, 18.92 % more performance-improvements than their peers, realized using the existing IMPLY, MAGIC-MUX designs, respectively. Also, our proposed-MUX based circuits need at least 56.73 % lesser crossbar-areas than their existing MAGIC-MUX based peers, which indicates the scope for large scale parallel processing inside a given memristive-memory.     

Current follower based reconfigurable integrator/differentiator circuits with passive and active components׳ reuse

Reconfigurable integrator/differentiator circuits based on the current follower are presented. They are essential for realizing configurable analog blocks (CABs) for field programmable analog arrays (FPAAs). The proposed circuits provide functional reconfigurations and components reuse. These functions provide flexibility in the area of filter design within CAB architectures. Circuits based on current follower have the potential to operate at higher frequency ranges and offer improved linearity over their counterparts based on the operational amplifier and transconductance amplifier, respectively. No switches are used in a signal path in order to avoid degrading the frequency response of the proposed circuits. A CMOS current follower realization compatible with implementation of the proposed designs is adopted. Experimental results obtained from a standard 0.35 µm CMOS process are provided.     

A Systems Approach to a Compatible Family of Linear Integrated Circuits

An efficient and rapid technique for developing a compatible family of custom integrated circuits for systems applications is described. The approach makes use of a general purpose functional block which can be readily wired into a number of integrated circuit configurations. Wire bonded interconnections are used in place of the usual metallized interconnections. This permits a convenient form factor for "breadboarding" integrated circuits, while maintaining approximately the same parasitic interactions which will be present in the final designs. In this way, interface problems between functional electronic blocks can be studied as they relate to overall systems performance. Quick wiring changes may be made to modify the integrated circuits and optimize system performance. Final design layouts are then made in the conventional manner. As an example of the use of this technique, a general purpose block is described which was used to generate a compatible family of linear integrated circuits used in the Apollo-LEM lunar television camera.     

CMOS blocks for on-chip RF test

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.     

The impact of scaling down to deep submicron on CMOS RF circuits

Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-μm CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations     

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.     

Comparative analysis of CMOS adders circuits based on 10 transistors

Development of digital signal processing devices has led to appearance of a series of CMOS circuit designs of arithmetic and logic blocks with a small number of transistors. In this paper we suggest a classification of full single-bit CMOS adders, circuits of which consist of 10 transistors. The comparison of main characteristics of adders has been carried out based on the results of circuit simulation for 0.18-micron MOS technology and the most promising implementations have been marked out.