Selection of dispatching rules on multiple dispatching decision points in real-time scheduling of a semiconductor wafer fabrication system

Semiconductor wafer fabrication involves one of the most complex manufacturing processes ever used. To control such complex systems, it is a challenge to determine appropriate dispatching strategies under various system conditions. Dispatching strategies are classified into two categories: a vehicle-initiated dispatching policy and a machine-initiated dispatching policy. Both policies are important to improve the system performance, especially for the real time control of the system. However, there has been little research focusing on combining them under various situations for the semiconductor manufacturing system. In addition, it is shown that no single dispatching strategy consistently dominates others in all situations. Therefore, the goal of this study is to develop a scheduler for selection of dispatching rules for dispatching decision variables in order to obtain the desired performance measures given by a user for each production interval. For the proposed methodology, simulation and competitive neural network approaches are used. The results of the study indicate that applying our methodology to obtaining a dispatching strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.     

Modelling and analysis of wafer fabrication scheduling via generalized stochastic Petri net and simulated annealing

Some of the important characteristics of the semiconductor wafer fabrication factories are re-entrant process flows, a dynamic and uncertain environment, stringent production control requirements, etc. that pose a major challenge to the scheduling decisions in integrated circuit wafer fabrication process. Keeping in view the high capital investment and quick response to the market changes, it is essential for the integrated circuit fabrication process to exercise effective control on its production operations so that production resources can be employed in a flexible and efficient manner. The present research has focussed on the development of a generalized stochastic Petri net model that faithfully captures dynamic behaviours such as re-entrant processing, machine failures, loading and unloading, etc., pertaining to wafer fabrication. A simulated annealing-based scheduling strategy using mean cycle time and tardiness as performance measures was also developed to obtain an efficient and robust schedule for a known hard problem. Analysis of variance was applied to examine the interaction effects of various scheduling rules and to identify the main as well as the interaction effects of dispatching rules, dispatching rules and set-up rules, and set-up rules and batching rules. Paired t-tests were applied to assess the performance of rule combinations for lot and batch scheduling. The proposed simulated annealing-based solution methodology was tested on a well-known data set adopted from the literature and its performance reveals that simulated annealing-based scheduling rules work better than existing rules in terms of the two performance measures mean cycle time and tardiness.     

A due-date based production control policy using WIP balance for implementation in semiconductor fabrications

Production control policies are critical in the re-entrant processes of semiconductor fabrication. Manufacturing control policies such as input dispatching rules, CONWIP, and optimization-based rules have been implemented according to the managerial objectives of the wafer fabrication line. When few semiconductor wafer fabrication facilities were available, and the semiconductor industry was a seller's market, fabrications were operated to achieve both a high rate of production and high utilization of equipment. With the availability of more fabrications and the gradual shift to a buyer's market, customer satisfaction became a major measure of performance in semiconductor manufacturing. In this paper, due-date based production control policies for semiconductor fabrications are suggested, and their performances evaluated. Target balance (TB) optimization models using production target, due-dates, and WIP (work-in-process) are presented. The evaluation result shows that the TB models perform better than the ones cited in the literature.     

The infrastructure of the timed EOPNs-based multiple-objective real-time scheduling system for 300 mm wafer fab

Modern semiconductor wafer fabrication systems are changing from 200?mm to 300?mm wafer processing, and with the dual promises of more chips per wafer and economy of scale, leading semiconductor manufacturers are attracted to developing and implementing 300?mm wafer fabs. However, in today's dynamic and competitive global market, a successful semiconductor manufacturer has to excel in multiple performance indices, such as manufacturing cycle time and on-time delivery, and simultaneously optimize these objectives to reach the best-compromised system achievement. To cope with this challenge, in this paper, the infrastructure of a timed EOPNs-based multiple-objective real-time scheduling system (MRSS) is proposed to tackle complex 300?mm wafer fabs. Four specific performance objectives pursued by contemporary semiconductor manufacturers are integrated into a priority-ranking algorithm, which can serve as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the real-time state-dependent dispatching system. This dispatching control system is timed EOPN-based and adopts a heterarchical organization that leads to a better real-time performance and adaptability. As the foundation of real-time schedule, the timed EOPNs modelling approach is expounded in detail, and the prototype of the MRSS simulation system is also provided.     

不确定环境下复杂机械装配系统设备维修方法

为保障不确定环境下复杂机械装配系统的连续性并降低其维修成本,提出一种以马尔可夫决策理论为基础的设备维修策略动态选择方法。在综合考虑系统运行成本、缓冲库存成本、设备维修成本及停机损失成本的基础上,构建了装配系统可靠性成本模型。该模型以带有中间缓冲区的二级装配系统为研究对象,以设备状态和缓冲库存量为自变量,以可靠性成本为目标函数。分析了装配系统的不同运行状态,利用模拟退火算法和模糊非线性混合整数目标规划对可靠性成本模型求解,制定装配系统最优维修方法。该方法降低了装配系统停机时间,减少了设备维修次数,可为生产线设计和维修计划的制定提供依据。最后,通过算例分析验证了模型的有效性和可行性。     

An optimised dynamic bottleneck dispatching policy for semiconductor wafer fabrication

A dynamic bottleneck dispatching (DBD) policy is designed in this paper to detect bottlenecks in a timely way and make adaptive dispatching decisions of semiconductor wafer fabrication systems according to the real-time conditions. Control parameters of the proposed DBD algorithm are optimised by response surface methodology (RSM) and desirability functions. Numerical results show that DBD outperforms common scheduling rules such as CR?+?FIFO, EDD, SRPT, SPT, SPNB and an existing dynamic bottleneck dispatching method.     

Scheduling policies in multi-product manufacturing systems with sequence-dependent setup times and finite buffers

Multi-product production systems with sequence-dependent setup times are typical in the manufacturing of semiconductor chips and other electronic products. In such systems, the scheduling policies coordinating the production of multiple product types play an important role. In this paper, we study a multi-product manufacturing system with finite buffers, sequence-dependent setup times and various scheduling policies. Using continuous-time Markov chain models, we evaluate the performance of such systems under seven scheduling policies, i.e. cyclic, shortest queue, shortest processing time, shortest overall time (including setup time and processing time), longest queue, longest processing time, and longest overall time. The impacts of these policies on system throughput are compared, and the conditions characterising the superiority of each policy are investigated. The results of this work can provide production engineers and supervisors practical guidance to operate multi-product manufacturing systems with sequence-dependent setups.     

Production policies under deteriorating process conditions

This paper examines a single-stage production system that manufactures multiple products under deteriorating equipment conditions. The machine condition worsens with production, and improves with maintenance. The condition of the process can be in any one of several discrete states, and transitions from state to state follow a semi-Markov process. In many production environments, the quality or yield of output depends heavily on the condition of the production process. The problem considers the trade-offs between manufacturing products that have a higher profit, a longer processing time, and therefore, a higher deterioration probability versus products that have a smaller profit, shorter processing time with a lower process deterioration probability. The firm needs to determine the optimal production choice in each state in a way that maximizes the long-run expected average reward per unit time.

The paper makes three sets of contributions. First, it introduces the concept of critical ratios for the firm's manufacturing decision at each state regarding whether to switch from one product to another. Second, through the use of critical ratios, the main result shows that the optimal production choice for each state can be determined independently of the actions taken in other states, despite the complex interconnections between the production decisions and state transitions. Third, the paper provides generalizations that illustrate the depth, scope and richness of the proposed solution technique by extending the model in the number of machine states, to settings where maintenance is performed in intermediate states, and to settings where transition probabilities are influenced by both mean and variance of processing times.     

Maintenance,shutdown and production scheduling in semiconductor robotic cells

Our approach is the first to study simultaneous scheduling of preventive maintenance, shutdowns and production for robotic cells in semiconductor manufacturing. It hereby exploits the frequent periods of overcapacity in semiconductor manufacturing to reduce wear and tear. In contrast to existing approaches, our scheduling approach is able to deal with different preventive-maintenance types. We borrow the Resource Task Network representation from the process-industry domain to represent our problem and facilitate its formulation as a mathematical model. In addition, we develop efficiency-improving constraints based on the characteristics of the preventive-maintenance activities. In numerical tests based on industry data, we show that the model generates high-quality schedules even without applying the inequalities, although the optimality gap is reduced only when including inequalities. We furthermore assess the trade-off between shutdowns and batch lead times. We compare our model’s schedule quality to (i) the simple industry practice of shutting down chambers permanently to reduce wear and tear and (ii) an approach that schedules maintenance and production sequentially. The numerical tests yield the following managerial insights. First, integrating maintenance and production scheduling has substantial advantages. Second, the practice of shutting equipment down permanently diminishes scheduling flexibility and solution quality. Third, shutdowns scheduling must also consider the impact on batch waiting times.     

基于AHP和规则的多目标晶圆制造派工方法的应用

针对半导体晶圆制造系统调度的时变多目标特性,提出基于AHP和规则的多目标派工方法,在不同时期,赋予各调度目标不同的权重,通过仿真实验得到判断矩阵,然后用层次分析法来选择各设备的派工规则,并进行了敏感性分析,为半导体晶圆制造系统的科学管理提供了有效的实现途径.     

Capacity-constrained scheduling for a logic IC final test facility

A capacity-constrained scheduling using the concept of the theory of constraints for a semiconductor Logic IC final test operation is presented. The scheduling of the IC final test considers unrelated parallel machines with multiple constraint problems. A broad product mix, variable lot sizes and yields, long and variable set-up times, as well as limited test equipment capacity characterize the operations in this test facility. Discrete event simulation models based on e-M-Plant? are developed to implement the capacity-constrained scheduling algorithm. A comparison is also made with other rules, which are combinations of the rules such as first come first serve and earliest due date for the order scheduling, and the rules such as minimum set-up time, shortest processing time and shortest set-up time plus processing time for the dispatching test equipment. The simulation results show that the proposed capacity-constrained scheduling outperforms other rules for the committed volume performance in many different operational conditions. Directions for future research are also presented.     

A simulation study of new multi-objective composite dispatching rules,CONWIP, and push lot release in semiconductor fabrication

This paper evaluates dispatching rules and order release policies in two wafer fabrication facilities (thereafter referred to as ‘fab’) representing ASIC (application specific integrated circuit) and low-mix high-volume production. Order release policies were fixed-interval (push) release, and constant work-in-process (CONWIP) (pull) policy. Following rigorous fab modelling and statistical analysis, new composite dispatching rules were found to be robust for average and variance of flow time, as well as due-date adherence measures, in both production modes.     

A new paradigm for rule-based scheduling in the wafer probe centre

This paper addresses the scheduling problem in the wafer probe centre. The proposed approach is based on the dispatching rule, which is popularly used in the semiconductor manufacturing industry. Instead of designing new rules, this paper proposes a new paradigm to utilize these rules. The proposed paradigm formulates the dispatching process as a 2-D assignment problem with the consideration of information from multiple lots and multiple pieces of equipment in an integrated manner. Then, the dispatching decisions are made by maximizing the gains of multiple possible decisions simultaneously. Besides, we develop a genetic algorithm (GA) for generating good dispatching rules through combining multiple rules with linear weighted summation. The benefits of the proposed paradigm and GA are verified with a comprehensive simulation study on three due-date-based performance measures. The experimental results show that under the proposed paradigm, the dispatching rules and GA can perform much better than under the traditional paradigm.     

Job order releasing and throughput planning for multi-priority orders in wafer fabs

To meet the production target of multi-level (multiple priority rank) orders in wafer fabs, this paper uses a hierarchical framework based on a mathematical model, and without the assistance of any simulation tool, to build a production scheduling system to plan wafer lot releasing sequence and time. This system first applies capacity loading analysis to set up the batch policy for each level (rank) of orders. Next, the production cycle time of each product level is estimated with considerations of batching and loading factor. The cycle time is then used to derive system control parameters such as the most appropriate level of work in process (WIP) and the number of daily operations on the bottleneck workstation. Lastly, a Constant WIP mechanism is applied to establish a wafer release sequence table and a throughput timetable. The due date designation for each specific order can hence be confirmed. With the comparison with the result of simulation, it shows that under the designed system the performance and planning measures in the master production schedule can be drawn up quickly and accurately, and the system throughput target and due date satisfaction can be achieved. Overall, the proposed production scheduling system is both effective and practicable, and the planning results are supportive for good target planning and production activity control.     

Simultaneous determination of preventive maintenance and replacement policies in a queue-like production system with minimal repair

This paper addresses the joint effects of preventive maintenance and replacement policies on a queue-like production system with minimal repair at failures. We consider a policy which calls for a preventive maintenance operation whenever N parts have been processed. If a failure occurs and at least K preventive maintenance operations have been carried out, the system is replaced by a new one. Otherwise, a failure is handled by minimal repair. An analytical model is developed and the argument of renewal–reward theory is used to provide long-run expected profit per unit time for a given maintenance and replacement policy. Numerical examples are given to provide some managerial insights.     

Scheduling policies,batch sizes,and manufacturing lead times

In this paper we examine the impact of scheduling policies on batch sizing decisions in a multi-item production system. We also investigate the joint effect of scheduling policies and batch sizing decisions on production lead times. In particular we compare the performance of a first-come-first-served (FCFS) policy with that of a group scheduling (GS) policy and study the effect of each on the optimal batch size. We show that a GS policy can lead to significant performance gains, as measured by reduced lead times and higher production rates, relative to the FCFS policy, and characterize conditions under which these gains are realized. We also study the impact of the GS policy on other system operating parameters. In particular we find that using a GS policy eliminates the need for batching, preserves system capacity despite the presence of setups, and accommodates higher product mix variety. These results are shown to be very different from those obtained for the FCFS policy and to have important implications for the management and control of multi-item production facilities.     

串联生产系统智能维护调度实验平台研究

结合工业工程专业学习需求,设计了考虑有限缓存的串联生产系统维护调度实验平台。实验平台由维护调度计算模块和维护调度演示模块组成。维护调度计算模块基于Matlab,在考虑有限缓存的串联生产系统维护调度模型的基础上,提供3种不同的策略对维护进行调度;维护调度演示模块基于Flexsim。基于该平台,可完成维护调度参数分析、维护调度策略分析、维护调度仿真等实验,并可在此平台基础上建立维护调度相关参数优化模型。     

Scheduling of wafer test processes in semiconductor manufacturing

This research focuses on solving a common wafer test scheduling problem in semiconductor manufacturing. During wafer testing, a series of test processes are conducted on wafers using computer-controlled test stations at various temperatures. The test processes are conducted in a specified order on a wafer lot, resulting in precedence constraints for the schedule. Furthermore, the assignment of the wafer lots to test stations and the sequence in which they are processed affects the time required to set up the test operations. Thus, the set-up times are sequence dependent. Four heuristics are developed to solve the test scheduling problem with the aim of minimizing the makespan required to test all wafers on a set of test stations. The heuristics generate a sorted list of wafer lots as a dispatching sequence and then schedule the wafer lots on test stations in order of appearance on the list. An experimental analysis and two case studies are presented to validate the proposed solution approaches. In the case studies, the heuristics are applied to actual data from a semiconductor manufacturing facility. For both case studies, the proposed solution approaches decrease the makespan by 23–45% compared with the makespan of the actual schedule executed in the manufacturing facility.     

Incorporating engineering process improvement activities into production planning formulations using a large-scale wafer fab model

In most semiconductor wafer fabrication facilities (wafer fabs), both production and engineering lots share the same expensive equipment. Production lots will be shipped to customers whereas engineering lots are used to support production and process development efforts. While production activities might lead to large revenue, engineering activities result in increased future output. In the present paper, we propose three different production planning formulations. The first formulation assumes a reduced available capacity for production due to engineering activities. Costs for production products are minimised. The second formulation is based on the idea that aggregated demand is available for engineering activities for the entire planning window. Costs for production and engineering products are minimised. Learning effects are incorporated to model the capacity increase due to engineering activities. The third model assumes that demand information for engineering activities is available only for the first period. In addition to learning effects, forgetting effects are modelled to provide an incentive to plan releases of engineering lots in later periods. Costs for production and engineering products and forgetting effects are minimised. The performance of the production planning models is assessed using a simulation model of a large-scale wafer fab including specific dispatching strategies to deal with production and engineering lots. The simulation results demonstrate that the second model slightly outperforms the third one when a rolling horizon approach is taken, while the second model provides significantly higher profit than the first one.     

Closed loop control-based real-time dispatching heuristic on parallel batch machines with incompatible job families and dynamic arrivals

In this paper, a real-time closed loop control dispatching heuristic (RCLC) algorithm is proposed to address the scheduling problem of parallel batch machines with incompatible job families, limited waiting time constraints, re-entrant flow and dynamic arrivals in the diffusion and oxidation areas of a semiconductor wafer fabrication system (SWFS), which is known to be strongly NP-hard. The basis of this algorithm is the information of lots in the buffer when the parallel batch machines are idle and available. In RCLC, if the number of any family lots is less than the maximum batch size, the dispatching heuristic can be seen as a pull–pull–push–push (P⁴) strategy; otherwise, a genetic algorithm (GA). A look-itself strategy, P⁴ strategy and GA can build a closed loop control system. The experiments are implemented on the Petri nets-based real-time scheduling simulation platform of SWFS, and demonstrate the effectiveness of our proposed method.