一种真空度可调的圆片级封装技术

提出了一种MEMS器件的圆片级封装技术。通过金硅键合和DRIE通孔制备等关键工艺技术,可以实现真空度从102 Pa到2个大气压可调的圆片级封装。作为工艺验证,成功实现了圆片级真空封装MEMS陀螺仪的样品制备。对封装后的陀螺仪样品进行了剪切力和品质因数Q值测试,剪切力测试结果证明封装样品键合强度达到5 kg以上,圆片级真空封装后陀螺的品质因数Q值约为75 000,对该陀螺的品质因数进行了历时1年的跟踪测试,在此期间品质因数Q的最大变化量小于7‰,品质因数测试结果表明封装具有较好的真空特性。     

采用MEMS工艺制作封装载体的LED封装技术

针对SiC衬底的白光LED技术研究和智能化半导体照明技术发展的需求,基于Si材料的功能特性和物理特性,研究了将Si作为SiC基LED封装载体的相关技术.采用MEMS的加工工艺,设计了精确尺寸的芯片安装腔体和高效率的反射层,抑制了Si本体材料对光的吸收,提高了芯片侧向光的导出效率.通过分析光窗形貌及封装胶折射率对白光LED光效的影响,给出了一个全新的SiC衬底的白光LED封装的技术路线,为LED芯片与驱动一体化封装的实现奠定了技术基础.实现了完整的加工过程和样品制备,测试表明光效大于130 lm/W,热阻小于4.6℃/W.     

毫米波相控阵封装天线电磁兼容仿真分析与设计

提出了一种毫米波相控阵封装天线的建模方法,通过商业仿真软件搭建了相控阵封装天线集数字、模拟和射频于一体的系统级仿真模型。基于此模型,分析了毫米波相控阵封装天线典型电磁兼容问题机理。此外,提出了相控阵封装天线电磁兼容设计的基本原则。原理样机试验和装机试飞验证了所提出的电磁兼容建模、仿真、分析和设计方法的有效性与正确性。     

再布线圆片级封装板级跌落可靠性研究

再布线圆片级封装通过对芯片焊区的重新构造以及无源元件的集成可以进一步提升封装密度、降低封装成本。再布线圆片级封装器件广泛应用于便携式设备中,在实际的装载、运输和使用过程中抗冲击可靠性受到高度重视。按照JEDEC标准对再布线圆片级封装样品进行了板级跌落试验,首先分析了器件在基板上不同组装点位的可靠性差异;然后依次探讨了不同节距和焊球尺寸、再布线结构对器件可靠性的影响;最后,对失效样品进行剖面制样,采用数字光学显微进行形貌表征。在此基础上,结合有限元分析对再布线结构和铜凸块结构的圆片级封装的可靠性和失效机理进行深入地阐释。     

封装过程中LED芯片理想因子的实验研究

基于发光二极管（LED）参数的非接触检测的方法研究,测试研究了封装过程中LED的理想因子。探讨了影响LED理想因子的因素,测试了光致发光（PL）条件下不同LED的理想因子,对比了封装缺陷对于理想因子的影响。实验表明,结温与载流子注入强度是LED理想因子的关键因素,LED封装过程中的缺陷对理想因子具有显著影响,并且可以通...     

一种基于低温共烧陶的无引线键合封装

为提高微机电系统(MEMS)加速度计的可靠性,减小因为引线键合断裂造成的传感器失效,该文设计了一种基于低温共烧陶瓷的无引线键合封装。该封装采用阳极键合技术将低温共烧陶瓷基板与芯片连接,同时将电路转接板同步集成。结果表明,该封装结构可减小传感器的封装尺寸,有效提高了MEMS加速度计的可靠性。     

有机电致发光器件的新型薄膜封装技术研究

针对有机电致发光器件(OLED)在空气中水汽和O2作用下寿命下降的问题,提出一种对OLED进行薄膜封装方法。封装薄膜由电子束蒸镀Al2O3薄膜和原子层沉积(ALD,atomic layer deposition)Al2O3薄膜相结合形成。利用Ca薄膜电学测试方法测定封装薄膜的水汽透过率(WVTR)。具体实现方法是,采用玻璃作为衬底,在100nm的Al电极上蒸镀200nm的Ca膜,然后对整个系统进行薄膜封装,只留出Al电极的一部分作为探针接触电极。实验发现,采用电子束蒸镀结合ALD的Al2O3薄膜封装,Ca薄膜变成透明的时间比未封装或采用单一结构封装得到了延长。为了检验薄膜封装效果,制作了一组绿光OLED,器件结构为ITO/MoOX(5nm)/mMTDATA(20nm)/NPB(30nm)/Alq3(50nm)/LiF(1nm)/Al,实验结果表明,本文提出的薄膜封装方法对器件进行封装,器件的寿命得到了延长。     

基于比特重排的减少机顶盒芯片DDR接口SSN的方法

封装电感引起的SSN(Simultaneous Switching Noise,同步开关噪音)效应阻碍低成本QFP(Quad Flat Package,四方型扁平式封装)封装的机顶盒芯片的DDR SDRAM(Double Data Rate Static Random Access Memory,双速率静态随机访问存储器,DDR)接口的传输频率.本文利用视频数据的相关性,及DDR颗粒的数据比特可以任意交换的特点,提出对DDR接口数据进行数据比特重排的方法来降低SSN效应.视频解码器使用到的数据在二维空间上高度相关.在DDR接口版图设计时将高比特位的数据与低比特位的数据在空间上交错放置,可使得DDR接口的电流分布更加平衡,减少通过封装寄生电感的平均电流,最终减少SSN.本文提出的方法成功用于台积电55rm工艺高清机顶盒芯片的设计.QFP封装的样片的DDR接口传输速率达到1066Mbps.     

MEMS传感器的封装

首先通过对MEMS封装所面临的挑战进行分析,提出了MEMS封装所需要考虑的一些问题。然后从芯片级、晶片级和系统级三个方面详细介绍了倒装焊、BGA、WLP、MCM和3D封装等先进的封装技术,并给出了一些应用这些封装方式对MEMS系统封装的实例。最后对MEMS和MEMS封装的走向进行了展望,并对全集成MEMS系统的封装进行了一些探讨。     

一种基于BCB键合技术的新型MEMS圆片级封装工艺

苯并环丁烯(BCB)键合技术通过光刻工艺可以直接实现图形化,相对于其他工艺途径具有工艺简单、容易实现图形化的优点。选用4000系列BCB材料进行MEMS传感器的粘接键合工艺试验,解决了圆片级封装问题,采用该技术成功加工出具有三层结构的圆片级封装某种惯性压阻类传感器。依据标准GJB548A对其进行了剪切强度和检漏测试,测得封装样品漏率小于5×10-3Pa.cm3/s,键合强度大于49N,满足考核要求。     

高密度封装进展之二——半导体封装技术的发展趋势

本文从超小型封装、超多端子封装、多芯片封装等几个方向介绍了半导体封装技术的发展趋势     

高密度封装进展之三——SiP与SoC

哪种方式更能提高LST的附加值?是SiP(system in a package)还是SoC(system on a chip)?LSI厂家正对此进行激烈争论。作为系统集成的选择方式,LSI厂家一直集中力量致力于SoC的开发。但是LSI厂家发现,仅靠SoC这一条路线已不能满足用户的要求。目前,对于各大LSI厂家来说,要不要转换其发展资源的投入方向,需要当机立断。     

Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs

An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm²) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm²/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.     

High-performance FCBGA based on multi-layer thin-substrate packaging technology

We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T_g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning.We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.     

芯片封装技术介绍

微电子技术的飞速发展也同时推动了新型芯片封装技术的研究和开发。本文主要介绍了几种芯片封装技术的特点,并对未来的发展趋势及方向进行了初步分析。     

先进芯片封装技术

微电子技术的飞速发展也同时推动了新型芯片封装技术的研究和开发。本文主要介绍了几种新型芯片封装技术的特点,并对未来的发展趋势及方向进行了初步分析。     

芯片封装技术介绍

微电子技术的飞速发展也同时推动了新型芯片封装技术的研究和开发.本文主要介绍了几种芯片封装技术的特点,并对未来的发展趋势及方向进行了初步分析.     

SIP的优势和展望

介绍了一种微系统集成的新技术-SIP，并将其与SoC进行了比较，阐述了SIP的优势和应用，指出SIP将会成为微系统集成技术带来更大的发展。     

Electroless Ni/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones

Wafer bumping technology using an electroless Ni/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni/Au bump. This study measures the shear forces on Ni/Au bumps prepared in different ways, showing that the suitable pretreatment protocol for electroless Ni plating on Cu pads is “acid dip followed by Pd activation” rather than the conventional progression of “acid-dip, microetching, and Pd activation.” The interface between the Cu pad and the Ni/Au bump is studied using various surface analysis methods. The homogeneous distribution of catalytic Pd on the Cu pad is first validated. The flip chip package structure is designed, assembled, and tested for reliability. The successful flip chip bonding in the CIS package is characterized in terms of the cross-sectional structure in which the anisotropic conductive film (ACF) particles are deformed to about 1.5 μm in diameter. The experimental results suggest that electroless Ni/Au can be applied to the flip chip type CIS package using Cu patterned wafers for high mega pixel applications.     

焊球阵列封装及其返修工艺技术

在简介各种焊球阵列(BGA)封装形式的基础上,归纳出BGA封装的技术优势,包括引脚结构、封装尺寸和封装密度等,并分析了BGA封装的返修工艺技术.分析结果表明,BGA封装进一步缩小了IC的封装尺寸,提高了高密度表面贴装技术水平,因而顺应了LSI和VLSI新品轻薄、短小及功能多样化的发展方向.