Submicrometer n+-Ge gate AlGaAs/GaAs MISFETs

Submicrometer n⁺-Ge gate AlGaAs/GaAs MISFETs have been developed by designing a fabrication process for the n⁺-implanted region. The short-channel effect was sufficiently suppressed by lowering the ion-implantation energy down to 50 keV to achieve a standard deviation of threshold voltage as small as 13 mV for 0.5-μm-gate FETs in a 2-in-diameter wafer. The source resistance was reduced by increasing the annealing temperature to 850°C to obtain a transconductance of 500 mS/mm for a 0.5-μm-gate FET. Even after annealing at such a high temperature, the quality of the channel layer was maintained at a sufficient level to realize a large cutoff frequency of 70 GHz for a 0.4-μm-gate FET. A divide-by-four static frequency divider was also fabricated using the above-mentioned fabrication technology. Successful operation at 16 GHz at 300 K was obtained with a divider using 0.9-μm-gate FETs at a low power dissipation of 36 mW per T-flip-flop     

A 70-GHz fT low operating bias self-aligned p-type SiGeMODFET

A self-aligned process for the fabrication of SiGe p-type modulation-doped field-effect transistors (MODFETs) is described. Self-aligned devices with 0.1-μm gate-length have been fabricated and characterized. A maximum dc extrinsic transconductance of 258 mS/mm was obtained with a low turn-on resistance and very low knee voltage. Excellent high frequency performance with a unity current-gain cutoff frequency (f_T) of 70 GHz was obtained. This excellent high frequency performance was exhibited even at drain bias as low as 0.5 V     

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 μm have been successfully fabricated with Au/WSiN refractory metal gate n⁺-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n⁺-contact regions was examined to reduce substrate leakage current. The 0.2-μm gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V     

Two-dimensional analysis of short-channel delta-doped GaAs MESFETs

Key design parameters for delta-doped GaAs MESFETs, such as delta doping profile, top layer background doping density, and scaling of lateral feature size, are investigated using a two-dimensional numerical simulation. A three-region (delta-doped conducting channel, top layer, and substrate) velocity-field relation is implemented in the model as appropriate for the particular device structure which is simulated. Simulation results show excellent agreement with a fabricated 0.5-μm gate-length delta-doped GaAs MESFETs based on atomic layer epitaxy material. An extrinsic transconductance of 370 mS/mm and a drain-source current of 270 mA/mm are obtained for typical devices, and the maximum transconductance is as high as 400 mS/mm. These are the best DC results yet reported for 0.5-μm gate-length delta-doped GaAs MESFETs. Considerations of design and optimization are discussed in terms of threshold voltage sensitivity, transconductance, current drive capability, and cutoff frequency, based on both simulation and experiment results     

Measurements of a fabricated micro mirror using a lateral-effectposition-sensitive photodiode

The characteristics of a fabricated micro mirror were determined using an optical measurement system. The system consisted of a helium-neon laser, a p-i-n lateral-effect photodiode, and other fundamental optical elements. For testing, we used a micro mirror array (1×4) in which each mirror was composed of a mirror plate, two torsional flexure hinges, two address electrodes, and two support posts. A mirror plate was designed to a size of 100×110×1.5 μm ³ and the hinge size was 20 μm long, 5 μm wide, and 0.5 μm thick. The micro mirror array was fabricated using micromachining technology and a lithography-galvanoformung-abformung-like process using nickel electroplating. The variation in the mirror's deflection angle with applied voltage was measured as a static characteristic. The downward threshold voltage of the 0.5-μm thick hinge was 48 V. The step response time, as a dynamic characteristic, was 21.8 μs when a 64 V step voltage higher than the downward threshold voltage was applied to an address electrode. The lifetime of the fabricated micro mirror was tested for both unidirectional and bidirectional operation     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Near-ideal I-V characteristics of GaInP/GaAsheterojunction bipolar transistors

GaInP/GaAs heterojunction bipolar transistors (HBTs) have been fabricated and these devices exhibit near-ideal I-V characteristics with very small magnitudes of the base-emitter junction space-charge recombination current. Measured current gains in both 6-μm×6-μm and 100-μm×100-μm devices remain constant for five decades of collector current and are greater than unity at ultrasmall current densities on the order of 1×10^-6 A/cm². For the 6-μm×6-μm device, the current gain reaches a high value of 190 at higher current levels. These device characteristics are also compared to published data of an abrupt AlGaAs/GaAs HBT having a base layer with similar doping level and thickness     

A low glitch 14-b 100-MHz D/A converter

A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (f_CLK) of 10 MHz and an output frequency (f_OUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices     

High-power temperature-insensitive gain-offset InGaAs/GaAsvertical-cavity surface-emitting lasers

The authors have grown 997 nm vertical-cavity surface-emitting lasers with an offset between the wavelength of the cavity mode and the quantum well gain peak to improve high temperature operation, and with higher aluminum-content barriers around the active region to improve the carrier confinement. They fabricated lasers of 8-15 and 20-μm diameters. The 8-μm-diameter devices exhibited CW operation up to 140°C with little change in threshold current from 15°C to 100°C, and the 20-μm-diameter devices showed CW output power of 11 mW at 25°C without significant heat sinking     

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance512-Mb single-level modes

A 116.7-mm² NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is fabricated with a 0.15-μm CMOS technology. Utilizing simultaneous operation of four independent banks, the device achieves 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes, respectively. The two-step bitline setup scheme suppresses the peak current below 60 mA. The wordline ramping technique avoids program disturbance. The SLC mode uses the 0.5-V incremental step pulse and self-boosting program inhibit scheme to achieve high program performance, and the MLC mode uses 0.15-V incremental step pulse and local self-boosting program inhibit scheme to tightly control the cell threshold voltage V_th distributions. With the small wordline and bitline pitches of 0.3-μm and 0.36-μm, respectively, the cell V_th shift due to the floating gate coupling is about 0.2 V. The read margins between adjacent two program states are optimized resulting in the nonuniform cell V_th distribution for MLC mode     

VTH-hopping scheme to reduce subthreshold leakage forlow-power processors

In order to suppress the power consumption in low-voltage processors, a threshold voltage hopping (V_TH-hopping) scheme is proposed where the threshold voltage is dynamically controlled through software depending on a workload. V_TH-hopping is shown to reduce the power to 18 % of the fixed low-threshold voltage circuits in 0.5-V supply voltage regime for multimedia applications. A positive back-gate bias scheme with V_TH-hopping is presented for the high-performance and low-voltage processors. In order to verify the effectiveness of V_TH-hopping, a small-scale RISC processor with V_TH-hopping capability and the positive back-gate bias scheme is fabricated in a 0.6-μm CMOS technology. MPEG4 encoding is simulated based on the measured data. The result shows that 86% power saving can be achieved by using V_TH-hopping compared with the fixed positive back-gate bias scheme     

0.2-μm fully-self-aligned Y-shaped gate HJFET's with reducedgate-fringing capacitance fabricated using collimated sputtering andelectroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-μm, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C_f^rext) of conventional Y-shaped gate HJFET's. The 0.2-μm Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO₂ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-μm gate n-Al_0.2Ga_0.8As/In_0.2Ga_0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm _max of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f_T=71 GHz and f_max=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C_f^rext. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's     

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm² die size and a 1.1 μm² effective cell size     

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

A current-mode bidirectional I/O buffer was designed, and the maximum effective bandwidth of 1.0 Gb/s per wire was obtained from measurements. To enhance the operating speed, the voltage swing on the transmission line was reduced to 0.5 V and the internal nodes of the buffer were designed to be low impedance nodes using the current-mode scheme. An automatic impedance-matching scheme was used to generate bias voltages, which adjust output resistance of the buffer to be equal to the characteristic impedance of the transmission line in spite of process variations. The chip was fabricated by using a 0.8-μm CMOS technology. The chip size was 500×330 μm², and the power consumption was 50 mW at a supply voltage of 3 V     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

1.55-μm buried-heterostructure VCSELs with InGaAsP/lnP-GaAs/AlAsDBRs on a GaAs substrate

We demonstrate 1.55-μm buried-heterostructure (BH) vertical-cavity surface-emitting lasers (VCSELs) on a GaAs substrate. Thin-film wafer-fusion technology enables InP-based BH VCSELs to be fabricated on GaAs/AlAs distributed Bragg reflectors. Detailed investigations of the device resistance are also described. As a result of introducing BH and obtaining low device resistance, the threshold current density under CW operation shows the independence of mesa size due to a strong index guide and small noneffective current. A 5-μm VCSEL exhibits a record threshold current of 380 μA at 20°C. This VCSEL also operates with single transverse mode up to the maximum optical output power     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

High-performance GaAs MESFETs with advanced LDD structure fordigital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-μm enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V_th=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-μm devices is less than 30 mV across a 3-in wafer. The 0.3-μm devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-μm device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-μm gate length devices operate above 10 Gb/s. In addition, the 0.3-μm devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications     

A 0.25-μm CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs     

GaInP/GaAs HBTs for high-speed integrated circuit applications

The use of GaInP/GaAs heterojunction bipolar transistors (HBTs) for integrated circuit applications is demonstrated. The discrete devices fabricated showed excellent DC characteristics with low V_ce offset voltage and very low temperature sensitivity of the current gain. For a non-self-aligned device with a 3-μm×1.4-μm emitter area, f_T was extrapolated to 45 GHz and f_max was extrapolated to 70 GHz. The measured 1/f noise level was 20 dB better than that of AlGaAs HBTs and comparable to that of low-noise silicon bipolar junction transistors, and the noise bump (Lorentzian component) was not observed. The fabricated gain block circuits showed 8.5 dB gain with a 3-dB bandwidth of 12 GHz, and static frequency dividers (divide by 4) were operable up to 8 GHz