平板显示器驱动芯片中NLDMOS寄生电容

功率器件寄生电容的大小直接关系到平板显示器驱动芯片的功耗及性能．本文利用器件的动态电流来分析NLDMOS寄生电容特性．在不影响NLDMOS直流特性的前提下,通过改变鸟嘴位置,得到具有低寄生电容的高性能器件．将该器件应用于平板显示器驱动芯片高低压转换电路,模拟结果证明该电路的自身功耗降低了34%,高压输出对低压控制信号的扰动减小了32%．     

Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1 V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18 µm TSMC technology parameters to verify the feasibility of the filter circuit.     

Ion-implanted ESFI MOS devices with short switching times

Switching times of complementary MOS devices realized with epitaxial silicon films on insulators (ESFI) are reduced by using a self-aligning technique with ion implantation, since the gate overlapping capacitances and therefore the so-called Miller capacitances, are reduced thereby. Switching times and power dissipation have been measured using multistage ring oscillators. Stage-delay times of 500 ps at a supply voltage of 10 V (800 ps at 5 V), and power-delay products of 0.5 pJ at 5 V, have been obtained at five-stage ring oscillators with a channel length of about 3 /spl mu/m. Calculated and measured results are compared, and a simple formula for calculating the influence of the Miller capacitance on the switching times is indicated.     

A low-power multi-mode and multi-output high-order CMOS universal Gm-C filter

This paper presents a new CMOS high-order Gm-C universal filter which can realize multi-mode (current, voltage, trans-resistance and trans-conductance) filtering functions, using grounded capacitors to absorbing shunt parasitic capacitances and a reduced number of active elements which leads to the minimum chip size and power consumption. Furthermore, in current-mode implementation, the proposed circuit produces simultaneously multiple filtering functions while uses just one configuration of inputs. Also, as the result of sensitivity analysis shows, the new filter structure has a very low sensitivity to the values of capacitors and trans-conductance elements. However, the proposed Gm-C filter is designed and simulated in HSPICE using 0.18 μm CMOS technology parameters and HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB which justifies the design accuracy and low-power, multi-mode, multi-output universal filtering performance of the proposed circuit.     

High-efficiency multiple-output DC-DC conversion for low-voltagesystems

This versatile power converter controller provides dual outputs at a fixed switching frequency and can regulate either output voltage or target system delay (using an external L-C filter). In the voltage regulation mode, the output voltage is monitored with an analog-digital (A/D) converter, and the feedback compensation network is implemented digitally. The generation of the pulsewidth modulation (PWM) signal is done with a hybrid delay line/counter approach, which saves power and area relative to previous implementations. Power devices are included on chip to create the two independently regulated output PWM signals. The key features of this design are its low-power dissipation, reconfigurability, use of either delay or voltage feedback, and multiple outputs     

CMOS multiplier for grounded capacitors

A CMOS circuit suited particularly to magnifying the value of a grounded unit capacitor is presented. The multiplication factor is achieved through the gain of current mirrors and its maximum value is limited solely by power consumption constraints. Solutions are then developed to reduce power dissipation, to enable the detection of small unit capacitances, and to enlarge the operating frequency bandwidth     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

Universal filter using plus-type CCIIs

A universal second-order filter circuit with voltage gain using only plus-type current conveyors (CCIIs) is presented. The circuit offers several advantages, such as high input impedance, low filter sensitivities to passive elements, use of grounded capacitors and independent control of ω₀, Q and voltage gain with separate grounded resistors. The use of only one type (plus-type or minus-type) of CCII simplifies the configuration     

基于介质电场增强理论的SOI横向高压器件与耐压模型

SOI(Silicon On Insulator)高压集成电路(High Voltage Integrated Circuit,HVIC)因其具有高速、低功耗、抗辐照以及易于隔离等优点而得以广泛应用。作为SOIHVIC的核心器件,SOI横向高压器件较低的纵向击穿电压,限制了其在高压功率集成电路中的应用。为此,国内外众多学者提出了一系列新结构以提高SOI横向高压器件的纵向耐压。但迄今为止,SOI横向高压器件均采用SiO2作为埋层,且实用SOI器件击穿电压不超过600V;同时,就SOI横向器件的电场分布和耐压解析模型而言,现有的模型仅针对具有均匀厚度埋氧层和均匀厚度漂移区的SOI器件建立,而且没有一个统一的理论来指导SOI横向高压器件的纵向耐压设计。笔者围绕SOI横向高压器件的耐压问题,从耐压理论、器件结构和耐压解析模型几方面进行了研究。基于SOI器件介质层电场临界化的思想,提出介质电场增强ENDIF(Enhanced Dielectric LayerField)理论。在ENDIF理论指导下,提出三类SOI横向高压器件新结构,建立相应的耐压解析模型,并进行实验。(1)ENDIF理论对现有典型横向SOI高压器件的纵向耐压机理统一化ENDIF理论的思想是通过增强埋层电场而提高SOI横向器件的纵向耐压。ENDIF理论给出了增强埋层电场的三种途径:采用低εr(相对介电常数)介质埋层、薄SOI层和在漂移区/埋层界面引入电荷,并获得了一维近似下埋层电场和器件耐压的解析式。ENDIF理论可对现有典型SOI横向高压器件的纵向耐压机理统一化,它突破了传统SOI横向器件纵向耐压的理论极限,是优化设计SOI横向高压器件纵向耐压的普适理论。(2)基于ENDIF理论,提出以下三类SOI横向高压器件新结构,并进行理论和实验研究①首次提出低εr型介质埋层SOI高压器件新型结构及其耐压解析模型低εr型介质埋层SOI高压器件包括低εr介质埋层SOI高压器件、变εr介质埋层SOI高压器件和低εr介质埋层PSOI(PartialSOI)高压器件。该类器件首次将低介电系数且高临界击穿电场的介质引入埋层或部分埋层,利用低εr介质增强埋层电场、变εr介质调制埋层和漂移区电场而提高器件耐压。通过求解二维Poisson方程,并考虑变εr介质对埋层和漂移区电场的调制作用,建立了变εr介质埋层SOI器件的耐压模型,由此获得RESURF判据。此模型和RESURF判据适用于变厚度埋层SOI器件和均匀介质埋层SOI器件,是变介质埋层SOI器件(包括变εr和变厚度介质埋层SOI器件)和均匀介质埋层SOI器件的统一耐压模型。借助解析模型和二维器件仿真软件MEDICI研究了器件电场分布和击穿电压与结构参数之间的关系。结果表明,变εr介质埋层SOI高压器件的埋层电场和器件耐压可比常规SOI器件分别提高一倍和83%,当源端埋层为高热导率的Si3N4而不是SiO2时,埋层电场和器件耐压分别提高73%和58%,且器件最高温度降低51%。解析结果和仿真结果吻合较好。②提出并成功研制电荷型介质场增强SOI高压器件笔者提出的电荷型介质场增强SOI高压器件包括:(a)双面电荷槽SOI高压器件和电荷槽PSOI高压器件,其在埋氧层的一侧或两侧形成介质槽。根据ENDIF理论,槽内束缚的电荷将增强埋层电场,进而提高器件耐压。电荷槽PSOI高压器件在提高耐压的基础上还能降低自热效应;(b)复合埋层SOI高压器件,其埋层由两层氧化物及其间多晶硅构成。该器件不仅利用两层埋氧承受耐压,而且多晶硅下界面的电荷增强第二埋氧层的电场,因而器件耐压提高。开发了基于SDB(Silicon Direct Bonding)技术的非平面埋氧层SOI材料的制备工艺,并研制出730V的双面电荷槽SOILDMOS和760V的复合埋层SOI器件,前者埋层电场从常规结构的低于120V/μm提高到300V/μm,后者第二埋氧层电场增至400V/μm以上。③提出薄硅层阶梯漂移区SOI高压器件新结构并建立其耐压解析模型该器件的漂移区厚度从源到漏阶梯增加。其原理是:在阶梯处引入新的电场峰,新电场峰调制漂移区电场并增强埋层电场,从而提高器件耐压。通过求解Poisson方程,建立阶梯漂移区SOI器件耐压解析模型。借助解析模型和数值仿真,研究了器件结构参数对电场分布和击穿电压的影响。结果表明:对tI=3μm,tS=0.5μm的2阶梯SOI器件,耐压比常规SOI结构提高一倍,且保持较低的导通电阻。仿真结果证实了解析模型的正确性。     

A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage readchannels

A monolithic active equalizer in 2-μm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations     

A micropower CMOS continuous-time filter with on-chip automatic tuning

This paper presents a CMOS implementation of a low-voltage micropower G/sub m/-C biquad with on-chip automatic tuning. The filter is suitable for any kind of application involving low-frequency ranges, and very low-power consumption, such as biomedical devices. The operational transconductance amplifier (OTA) is implemented with the transistors working in the weak inversion saturation region, thus allowing the use of very small currents that minimize the power consumption. The aspect ratios are small enough not to degrade the frequency response. The tuning algorithm is based on amplitude tracking. The filter output amplitude is quantized using a low-power amplifier and an asymmetric comparator. A digital controller varies the tuning parameters until the maximum quantized amplitude is found. The system works down to a voltage supply of 1.75 V. The center frequency is tunable over one and a half decades, from 300 Hz to 10 kHz for bias currents changing from 6 to 200 nA and a 20-pF integrating capacitance, giving an overall filter accuracy of up to 99.55%. The power consumption of the second-order filter including the common-mode correction circuitry is in the order of 200 nW for the 10-nA bias current. It exhibits a dynamic range of 54 dB and occupies an area of 0.06 mm/sup 2/ excluding the area of the integrating capacitances.     

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power tran-sistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obvi-ously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.     

Analytical Synthesis of Low-Sensitivity High-Order Voltage-Mode DDCC and FDCCII-Grounded R and C All-Pass Filter Structures

The difficulty of realizing the operations of addition and subtraction of a voltage-mode signal renders two special active elements, namely, differential difference current conveyors (DDCCs) and fully differential current conveyors (FDCCIIs), both of which have the ability to perform the operations of addition and subtraction, to become very important for voltage-mode analog filter design. Note that, for the design of operational transconductance amplifier and capacitor (OTA-C) filters, the recently reported analytical synthesis methods (ASMs) have been shown to be very effective for achieving simultaneously the three criteria, namely, all capacitors being grounded, the use of the minimum number of active and passive components, and the use of single-ended input OTAs. However, none of the ASMs uses DDCCs and FDCCIIs in the design of voltage-mode filters. In this paper, a method of realizing DDCC and FDCCII-based all-pass filter structures with either equal capacitances or equal conductances through a new ASM is presented. Only n current conveyors (the least number of active components), n grounded capacitors, and grounded resistors (the minimum number of passive components) are used for realizing an nth-order voltage-mode all-pass filter structure. Moreover, the new all-pass filter structure synthesized by the new ASM achieves very low individual as well as near-null group sensitivities just as in the case of the passive LC ladder filters, has very low power consumption, a low component spread for equal denominator conductance design, and a high input impedance which is attractive from the point of view of cascadability. Finally, H-Spice simulations, using 0.35-mum process and plusmn1.65-V supply voltages, are included and validate theoretical predictions.     

A 1?mW power-efficient high frequency CML 2:1 divider

In this study, a low power high operating frequency current mode logic (CML) 2:1 divider is presented. Because the latching transistor pair is biased in low current mode, the proposed divider is power-saving. In this divider, each latch has only one clock transistor, which means that the capacitive load to the former stages is reduced. This makes the buffer of the voltage controlled oscillator (VCO) or VCO be easily designed in phase locked loops. Besides, an active inductor is used in this circuit to resonate with parasitic capacitances and thus endows this topology a high-speed capability. The measurement results indicate that the proposed divider achieves an operation band from 10 to 15?GHz with only 1mW power dissipation.     

TLP和VFTLP应力下高压LDMOS的触发特性研究

本文通过TCAD软件－Sentaurus Device工具, 基于文献[1]所提出的一套物理宏模型进行仿真,研究了高压LDMOS功率器件（击穿电压大于160伏）在传输线脉冲和快速传输线脉冲应力下的静电放电（ESD）触发物理机制,发现在快速传输线脉冲应力下,高压LDMOS的触发电压有明显的提高,这一现象和低压普通静电放电保护器件（如NMOS器件和SCR器件）有明显的差异。本文详细分析了触发电压的上升现象和寄生电容的关系,并且用一个简单的等效电路原理图分析了上述现象。最后,本文提出了一种能够减轻触发电压上升这一现象的改进结构,并且得到了测试结果的验证。     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

Bus-invert coding for low-power I/O

Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling