A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

Highly Integrated Ka-Band Sub-Harmonic Image-Reject Down-Converter MMIC

An integrated compact down-converter monolithic microwave integrated circuit chip is presented. It is designed using anti-parallel diode pair sub-harmonic image reject mixer and RF low noise amplifier. The quasi-lumped circuit components are employed in circuit design for the compact chip size. The conversion gain of the chip is 10–14 dB, image rejection above 20 dBc, and noise figure of 3.5–4.5 dB for the RF frequency of 29–36 GHz. The chip size is as compact as $2.24~{rm mm}^{2}$ on a $100~mu{rm m}$ GaAs substrate thickness.      

High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.     

S-band low noise amplifier using 1 μm InGaAs/InAlAs/InP pHEMT

This paper discusses the design of a wideband low noise amplifier (LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications. The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT. Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz. A common-drain in cascade with a common source inductive degeneration, broadband LNA topology is proposed for wideband applications. The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss (S₁₁ < -10 dB, S₂₂ < -11 dB). This LNA exhibits an input 1-dB compression point of -18 dBm, a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

A 410-mW 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable applications

A 1.22-GHz downconverter used in a dual-conversion tuner IC for OpenCable applications is presented. The downconverter is configured as an image-reject receiver and utilizes a trifilar transformer in conjunction with capacitively cross-coupled common-gate mixer input stages to achieve a large dynamic range with relatively low power consumption. Fabricated in a five-metal 0.35-/spl mu/m, 27-GHz f/sub T/, silicon-on-insulator BiCMOS technology and consuming 124 mA from a 3.3-V supply, it downconverts the input to an IF of 44 MHz and achieves 26-dB gain, 23-dB gain control range, 5.1-dB noise figure, 33-dBmV P/sub 1dB/, 56-dBmV IIP/sub 3/, -72-dBc composite triple beat (CTB), -60-dBc cross-modulation, and 30-dB image rejection.     

An Implantable CMOS Amplifier for Nerve Signals

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 m CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/ . The amplifier power consumption is 275 W, drawn from a power supply; V _DD = –V _SS = 1.5 V.     

12-GHz-Band GaAs Dual-Gate MESFET Monolithic Mixers

12-GHz-band GaAs dual-gate MESFET monolithic mixers have been developed for use in direct broadcasting satellite receivers. In order to reduce chip size, a buffer amplifier has been connected directly after a mixer IF port, instead of employing an IF matching circuit. The mixer and the buffer were fabricated on separate chips, so that individual measurements could be achieved. Chip size is 0.96X 1.26 mm for the mixer and 0.96X0.60 mm for the buffer. A dual-gate FET for the mixer, as well as a single-gate FET for the buffer, has a closely spaced electrode structure. Gate length and width are 1 µm and 320 µm, respectively. The mixer with the buffer provides 2.9+-0.4-dB conversion gain with 12.3+-0.3dB SSB noise figure in the 11.7-12.2-GHz RF band. Local oscillator (LO) frequency is 10.8 GHz. A low-noise converter was constructed by connecting a monolithic preamplifier, an image rejection filter, and a monolithic IF amplifier to the mixer. The converter provides 46.8+-1.5-dB conversion gain with 2.8+-0.2-dB SSB noise figure in the same frequency band.     

GaAs Monolithic MIC's for Direct Broadcast Satellite Receivers

A 12-GHz low-noise amplifier (LNA), a 1-GHz IF amplifier (IFA), and an 11-GHz dielectric resonator oscillator (DRO) have been developed for DBS home receiver applications by using GaAs monolithic microwave integrated circuit (MMIC) technology. Each MMIC chip contains FET's as active elements and self-biasing source resistors and bypass capacitors for a single power supply operation. It also contairns dc-block and RF-bypass capacitors. The three-stage LNA exhibits a 3.4-dB noise figure and a 19.5-dB gain over 11.7-12.2 GHz. The negative-feedback-type three-stage IFA shows a 3.9-dB noise figure and a 23-dB gain over 0.5-1.5 GHz. The DRO gives 10.mW output power at 10.67 GHz, with a frequency stability of 1.5 MHz over a temperature range from -40-80°C. A direct broadcast satellite (DBS) receiver incorporating these MMIC's exhibits an overafl noise figure of /spl les/ 4.0 dB for frequencies from 11.7-12.2 GHz.     

一种S波段平衡式限幅低噪声放大器的设计

介绍了一种小型化平衡式限幅低噪声放大器。该放大器采用Lange桥平衡结构,在实现低噪声的同时,保证了小电压驻波比;在3.0～3.5GHz频带内,噪声系数小于1.3dB,输入输出驻波系数小于1.3,增益大于27dB,平坦度±0.6dB以内,输出1dB压缩点大于12dBm。该放大器能够承受最大5W的连续波功率输入,且大功率输入时的驻波系数小于1.3。     

A 30-GHz monolithic receiver

Several monolithic integrated circuits have been developed to make a 30-GHz receiver. The receiver components include a low-noise amplifier, an IF amplifier, a mixer, and a phase shifter. The LNA has a 7-dB noise figure with over 17 dB of associated gain. The IF amplifier has a 13-dB gain with a 30-dB control range. The mixer has a conversion loss of 10.5 dB. The phase shifter has a 180° phase shift control and a minimum insertion loss of 1.6 dB.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

Low-noise intelligent cladding-pumped L-band EDFA

We present results on a low-cost cladding-pumped L-band amplifier based on side pumping (GTWave) fiber technology and pumped by a single 980-nm multimode diode. We show that simultaneous noise reduction and transient suppression can be achieved by using gain clamping by a seed signal (/spl lambda/=1564 nm). In the gain-clamping regime, the amplifier exhibits 30-dB gain over 1570-1605-nm spectral band with noise figure below 7 dB. The noise figure can be further reduced to below 5 dB by utilizing a low power single-mode pump at 980 nm. The erbium-doped fiber amplifier is relatively insensitive to input signal variations with power excursions below 0.15 dB for a 10-dB channel add-drop.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

A gm-boosted common-gate CMOS low-noise amplifier with high P1dB

A 2.4-GHz transconductance (g_m)—boosted common gate (CG) low-noise amplifier (LNA) with a high 1-dB compression point (P1dB) is proposed. To overcome the constraint of conventional CG LNA for input-mismatching, RF filters consisting of band-stop and high-pass filter are used as a load and inter-stage matching components, respectively. Therefore, the g _m can be freely increased for a high gain and low noise figure (NF) without decreasing input impedance. Moreover, the linearity is also enhanced because band-stop filter load can reduce 2nd harmonics. The fully integrated LNA implemented by 0.18-µm RF CMOS technology delivers an input P1dB of ?1 dBm, a power gain of 14.8 dB and a NF of 3.7 dB. The LNA consumes 8.2 mA at a supply voltage of 1.8 V.     

Design and Performance of Microwave Amplifiers with GaAs Schottky-Gate Field-Effect Transistors

The design and performance of an X-band amplifier with GaAs Schottky-gate field-effect transistors are described. The amplifier achieves 20 /spl plusmn/ 1.3-dB gain with a 5.5-dB typical noise figure (6.9 dB maximum) over the frequency range of 8.0-12.0 GHz. The VSWR at the input and output ports does not exceed 2.5:1. The minimum output power for 1-dB gain compression is +13 dBm, and the intercept point for third-order intermodulation products is +26 dBm. The design of practical wide-band coupling networks is discussed. These networks minimize the overall amplifier noise figure and maintain a constant gain in the band.     

Analysis of optical amplifier noise in coherent opticalcommunication systems with optical image rejection receivers

A detailed theoretical analysis of optical amplifier noise in coherent optical communication systems with heterodyne receivers is presented. The analysis quantifies in particular how optical image rejection receiver configurations reduce the influence of optical amplifier noise on system performance. Two types of optical image rejection receivers are investigated: a novel, all-optical configuration and the conventional, microwave-based configuration. The analysis shows that local oscillator-spontaneous emission beat noise (LO-SP), signal-spontaneous emission beat noise (S-SP), and spontaneous-spontaneous beat noise (SP-SP) can all be reduced by 3 dB, thereby doubling the dynamic range of the optical amplifier. A 2.5-dB improvement in dynamic range has been demonstrated experimentally with the all-optical image rejection configuration. The implications of the increased dynamic range thus obtained are also discussed from a systems point of view     

60-GHz noise performance of ion-implanted InxGa1-xAs MESFET's

The authors report the 60-GHz noise performance of low-noise ion-implanted In_xGa_1-xAs MESFETs with 0.25 μm T-shaped gates and amplifiers using these devices. The device noise figure was 2.8 dB with an associated gain of 5.6 dB at 60 GHz. A hybrid two-state amplifier using these ion-implanted In_xGa_1-x As MESFETs achieved a noise figure of 4.6 dB with an associated gain of 10.1 dB at 60 GHz. When this amplifier was biased at 100% I _dss, it achieved 11.5-dB gain at 60 GHz. These results, achieved using low-cost ion-implantation techniques, are the best reported noise figures for ion-implanted MESFETs